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1. 发明授权

US11869603B2 Voltage regulation 有权
公开(公告)号：US11869603B2
公开(公告)日：2024-01-09
申请号：US17401524
申请日：2021-08-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Shuai Xu , Michele Piccardi , June Lee
IPC分类号： G11C16/30 , G05F1/575 , G11C16/04
CPC分类号： G11C16/30 , G05F1/575 , G11C16/0483
摘要： Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

2. 发明授权

US09613706B2 Programming and/or erasing a memory device in response to its program and/or erase history 有权
公开(公告)号：US09613706B2
公开(公告)日：2017-04-04
申请号：US15059457
申请日：2016-03-03
申请人： MICRON TECHNOLOGY, INC.
发明人： June Lee , Fred Jaffin, III
IPC分类号： G11C16/04 , G11C16/14 , G11C16/26 , G06F11/10 , G11C11/56 , G11C16/10 , G11C16/20 , G11C16/34
CPC分类号： G11C16/12 , G06F11/1068 , G06F2212/202 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/20 , G11C16/26 , G11C16/349
摘要： A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number of program/erase cycles has been previously applied to one or more memory cells of an array of memory cells of the memory device, using the counter to increment the number of program/erase cycles each time an additional program/erase cycle is applied to the one or more memory cells, using compare logic of the control logic to compare the incremented number of program/erase cycles to a numerical value, and using starting-voltage level control logic of the control logic to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the numerical value.

3. 发明申请

US20140153335A1 ASYNCHRONOUS/SYNCHRONOUS INTERFACE 有权
标题翻译：异步/同步接口
公开(公告)号：US20140153335A1
公开(公告)日：2014-06-05
申请号：US14063773
申请日：2013-10-25
申请人： Micron Technology, Inc.
发明人： Dean K. Nobunaga , June Lee , Chih Liang Chen
IPC分类号： G11C16/10
CPC分类号： G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
摘要： The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
摘要翻译：本公开包括用于操作存储器件的方法和电路。用于操作存储器件的一个方法实施例包括通过至少部分地响应于第一接口触点上的写入使能信号向存储器件写入数据来控制通过异步模式的存储器接口的数据传输，以及从存储器件读取数据至少部分地响应于第二接口触点上的读使能信号。该方法还包括通过至少部分地响应于第一接口触点上的时钟信号传送数据，并且在不在异步模式下使用的接口触点上提供双向数据选通信号，来以同步模式控制数据传输。

4. 发明申请

US20230059543A1 INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE 有权
公开(公告)号：US20230059543A1
公开(公告)日：2023-02-23
申请号：US17887940
申请日：2022-08-15
申请人： Micron Technology, Inc.
发明人： Andrea Giovanni Xotta , Dheeraj Srinivasan , Ali Mohammadzadeh , Karl D. Schuh , Guido Luciano Rizzo , Jung Sheng Hoei , Michele Piccardi , Tommaso Vali , Umberto Siciliani , Rohitkumar Makhija , June Lee , Aaron S. Yip , Daniel J. Hubbard
IPC分类号： G06F3/06
摘要： A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

5. 发明申请

US20180366166A1 ASYNCHRONOUS/SYNCHRONOUS INTERFACE 审中-公开
公开(公告)号：US20180366166A1
公开(公告)日：2018-12-20
申请号：US16110294
申请日：2018-08-23
申请人： Micron Technology, Inc.
发明人： Dean K. Nobunaga , June Lee , Chih Liang Chen
IPC分类号： G11C7/10 , G11C14/00 , G11C7/22 , G11C16/10 , G06F13/16
CPC分类号： G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
摘要： The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

6. 发明授权

US09959931B2 Programming a memory device in response to its program history 有权
公开(公告)号：US09959931B2
公开(公告)日：2018-05-01
申请号：US15440430
申请日：2017-02-23
申请人： MICRON TECHNOLOGY, INC.
发明人： June Lee , Fred Jaffin, III
IPC分类号： G11C11/34 , G11C16/12 , G11C16/04
CPC分类号： G11C16/12 , G06F11/1068 , G06F2212/202 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/20 , G11C16/26 , G11C16/349
摘要： A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during a first programming operation, comparing the determined number of program pulses required to program the sample of memory cells of the memory device to a target number of program pulses, and adjusting a program starting voltage level of one or more program pulses applied to one or more memory cells of the sample of memory cells during a second programming operation subsequent to the first programming operation when the determined number of program pulses required to program the sample of memory cells in the first programming operation is different than the target number so that the number of program pulses applied during the second programming operation tends toward the target number.

7. 发明授权

US12068240B2 Capacitor in a three-dimensional memory structure 有权
公开(公告)号：US12068240B2
公开(公告)日：2024-08-20
申请号：US17461435
申请日：2021-08-30
申请人： Micron Technology, Inc.
发明人： Xiaojiang Guo , Naveen Kaushik , Shuai Xu , June Lee
IPC分类号： H01L23/52 , H01L23/522 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
CPC分类号： H01L23/5223 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
摘要： Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

8. 发明授权

US12027227B2 Low power management for sleep mode operation of a memory device 有权
公开(公告)号：US12027227B2
公开(公告)日：2024-07-02
申请号：US17426963
申请日：2020-12-22
申请人： MICRON TECHNOLOGY, INC.
发明人： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC分类号： G11C5/14
CPC分类号： G11C5/144 , G11C5/147 , G11C5/148
摘要： A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

9. 发明公开

US20240071505A1 DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY 审中-公开
公开(公告)号：US20240071505A1
公开(公告)日：2024-02-29
申请号：US18237815
申请日：2023-08-24
申请人： Micron Technology, Inc.
发明人： Jiewei Chen , Mithun Kumar Ramasahayam , Tomoko Ogura Iwasaki , June Lee , Luyen Vu
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/3459
摘要： Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

10. 发明申请

US20230046421A1 VOLTAGE REGULATION 有权
公开(公告)号：US20230046421A1
公开(公告)日：2023-02-16
申请号：US17401524
申请日：2021-08-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Shuai Xu , Michele Piccardi , June Lee
IPC分类号： G11C16/30 , G05F1/575
摘要： Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

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