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1. 发明授权

US10049756B2 Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source 有权
公开(公告)号：US10049756B2
公开(公告)日：2018-08-14
申请号：US15478312
申请日：2017-04-04
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04
摘要： A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The data line is biased to a first potential greater than a second potential to which the source is biased and a select gate coupled between the second string of memory cells and the data line is deactivated during a programming operation performed on the selected memory cell. The programming operation includes applying a programming potential to a control gate of the selected memory cell concurrently with biasing the data line to the first potential and biasing the source to the second potential while the select gate is deactivated.

2. 发明申请

US20170206977A1 MEMORY DEVICES THAT APPLY A PROGRAMMING POTENTIAL TO A MEMORY CELL IN A STRING COUPLED TO A SOURCE AND DATA LINE CONCURRENTLY WITH BIASING THE DATA LINE TO A GREATER POTENTIAL THAN THE SOURCE 审中-公开
公开(公告)号：US20170206977A1
公开(公告)日：2017-07-20
申请号：US15478312
申请日：2017-04-04
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/34 , G11C16/10 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The data line is biased to a first potential greater than a second potential to which the source is biased and a select gate coupled between the second string of memory cells and the data line is deactivated during a programming operation performed on the selected memory cell. The programming operation includes applying a programming potential to a control gate of the selected memory cell concurrently with biasing the data line to the first potential and biasing the source to the second potential while the select gate is deactivated.

3. 发明授权

US10438672B2 Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming 有权
公开(公告)号：US10438672B2
公开(公告)日：2019-10-08
申请号：US16035857
申请日：2018-07-16
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04
摘要： Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.

4. 发明授权

US09646702B2 Operating memory devices to apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source 有权
公开(公告)号：US09646702B2
公开(公告)日：2017-05-09
申请号：US14995302
申请日：2016-01-14
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.

5. 发明申请

US20160365152A1 PROGRAMMING METHODS AND MEMORIES 有权
标题翻译：编程方法和记忆
公开(公告)号：US20160365152A1
公开(公告)日：2016-12-15
申请号：US15248130
申请日：2016-08-26
申请人： MICRON TECHNOLOGY, INC.
发明人： Yijie Zhao , Akira Goda
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： A method of programming a memory includes boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line, and when a criteria is met, reducing the channel voltage to a reduced voltage level and subsequently boosting the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line. Differences between the channel voltage boosted while the first portion of the plurality of increasing programming pulses is applied and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage boosted while the second portion of the plurality of increasing programming pulses is applied and voltages of the second portion of the plurality of increasing programming pulses.
摘要翻译：一种对存储器进行编程的方法包括：在多个递增的编程脉冲的第一部分被施加到所选择的存取线的同时升高通道电压，并且当满足标准时，将通道电压降低到降低的电压电平，沟道电压，从降低的电压电平开始，而多个增加的编程脉冲的第二部分被施加到所选择的存取线。当多个递增的编程脉冲的第一部分被施加时，增加的通道电压与多个递增的编程脉冲的第一部分的电压之间的差异基本上与在多个增加编程脉冲的第二部分之间升高的通道电压之间的差值相同施加增加的编程脉冲和多个递增编程脉冲的第二部分的电压。

6. 发明申请

US20160133327A1 MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的存储器件和偏置方法
公开(公告)号：US20160133327A1
公开(公告)日：2016-05-12
申请号：US14995302
申请日：2016-01-14
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.
摘要翻译：存储器件中的偏置方法便于存储器件编程操作。在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的第一串存储器单元被耦合到公共数据线和公共源，其中数据线被偏置到大于电位的电位在对所选择的存储单元执行的编程操作期间，源偏置。

7. 发明申请

US20150170757A1 PROGRAMMING MEMORIES AND METHODS 有权
标题翻译：编程记忆和方法
公开(公告)号：US20150170757A1
公开(公告)日：2015-06-18
申请号：US14633287
申请日：2015-02-27
申请人： MICRON TECHNOLOGY, INC.
发明人： Yijie Zhao , Akira Goda
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.
摘要翻译：公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。

8. 发明授权

US10325661B2 Methods of programming memory 有权
公开(公告)号：US10325661B2
公开(公告)日：2019-06-18
申请号：US15686510
申请日：2017-08-25
申请人： MICRON TECHNOLOGY, INC.
发明人： Yijie Zhao , Akira Goda
IPC分类号： G11C11/34 , G11C16/12 , G11C16/04 , G11C16/10 , G11C16/34
摘要： Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

9. 发明申请

US20180322933A1 MEMORY DEVICES AND APPARATUS CONFIGURED TO APPLY POSITIVE VOLTAGE LEVELS TO DATA LINES FOR MEMORY CELLS SELECTED FOR AND INHIBITED FROM PROGRAMMING 审中-公开
公开(公告)号：US20180322933A1
公开(公告)日：2018-11-08
申请号：US16035857
申请日：2018-07-16
申请人： MICRON TECHNOLOGY, INC.
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/34 , G11C16/04 , G11C16/10
摘要： Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.

10. 发明授权

US09754671B2 Programming methods and memories 有权
公开(公告)号：US09754671B2
公开(公告)日：2017-09-05
申请号：US15248130
申请日：2016-08-26
申请人： MICRON TECHNOLOGY, INC.
发明人： Yijie Zhao , Akira Goda
IPC分类号： G11C16/00 , G11C16/12 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： A method of programming a memory includes boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line, and when a criteria is met, reducing the channel voltage to a reduced voltage level and subsequently boosting the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line. Differences between the channel voltage boosted while the first portion of the plurality of increasing programming pulses is applied and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage boosted while the second portion of the plurality of increasing programming pulses is applied and voltages of the second portion of the plurality of increasing programming pulses.

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