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1. 发明申请

US20100169599A1 Security management in system with secure memory secrets 有权
标题翻译：具有安全内存秘密的系统中的安全管理
公开(公告)号：US20100169599A1
公开(公告)日：2010-07-01
申请号：US12319193
申请日：2008-12-31
申请人： Mahesh Natu , Shamanna Datta
发明人： Mahesh Natu , Shamanna Datta
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/1433 , G06F21/71
摘要： In some embodiments a Trusted Platform Module (TPM) manages a first flag that identifies whether a secure environment has ever been established. A chipset manages a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred. At least one processor and/or the chipset lock, maintain a lock, and/or unlock a memory in response to the second flag. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，可信平台模块（TPM）管理标识安全环境是否已建立的第一标志。一个芯片组管理一个第二个标志，标识出可能存在内存中的秘密，并发生复位或电源故障。响应于第二标志，至少一个处理器和/或芯片组锁定，保持锁定和/或解锁存储器。描述和要求保护其他实施例。

2. 发明授权

US08392985B2 Security management in system with secure memory secrets 有权
标题翻译：具有安全内存秘密的系统中的安全管理
公开(公告)号：US08392985B2
公开(公告)日：2013-03-05
申请号：US12319193
申请日：2008-12-31
申请人： Mahesh Natu , Shamanna Datta
发明人： Mahesh Natu , Shamanna Datta
IPC分类号： H04L29/06
CPC分类号： G06F12/1433 , G06F21/71
摘要： In some embodiments a Trusted Platform Module (TPM) manages a first flag that identifies whether a secure environment has ever been established. A chipset manages a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred. At least one processor and/or the chipset lock, maintain a lock, and/or unlock a memory in response to the second flag. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，可信平台模块（TPM）管理标识安全环境是否已建立的第一标志。一个芯片组管理一个第二个标志，标识出可能存在内存中的秘密，并发生复位或电源故障。响应于第二标志，至少一个处理器和/或芯片组锁定，保持锁定和/或解锁存储器。描述和要求保护其他实施例。

3. 发明授权

US5835704A Method of testing system memory 失效
标题翻译：系统内存测试方法
公开(公告)号：US5835704A
公开(公告)日：1998-11-10
申请号：US744625
申请日：1996-11-06
申请人： Yan Li , Mahesh Natu
发明人： Yan Li , Mahesh Natu
IPC分类号： G06F11/10 , G06F12/08 , G11C29/08 , G06F13/28
CPC分类号： G06F11/1008 , G11C29/08 , G06F12/0802 , G11C2029/0401 , G11C2029/0407
摘要： A method of testing at least a selected portion of system memory for a microprocessor system is disclosed, the microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus. The method includes the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written.
摘要翻译：公开了一种用于测试微处理器系统的至少一部分系统存储器的方法，该微处理器系统具有突发模式能力，以经由系统总线在微处理器和系统存储器之间传送数据值。该方法包括以下步骤：使用微处理器系统的突发模式能力，用预定的测试模式写入系统存储器的至少一部分; 使用微处理器系统的突发模式能力从系统存储器的至少一个选定部分读回值; 以及将从系统存储器的至少一个选定部分读取的值与所写入的预定测试图案进行比较。

4. 发明授权

US09411762B2 Method and system for platform management messages across peripheral component interconnect express (PCIe) segments 有权
标题翻译：跨平台管理消息的方法和系统，跨外围组件互连快速（PCIe）段
公开(公告)号：US09411762B2
公开(公告)日：2016-08-09
申请号：US13843066
申请日：2013-03-15
申请人： Mahesh Natu , Mohan Nair
发明人： Mahesh Natu , Mohan Nair
IPC分类号： G06F12/06 , G06F13/40 , G06F13/38
CPC分类号： G06F13/385 , G06F12/06
摘要： A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.
摘要翻译：公开了一种通过在计算系统的根复合体上实现的多个外围组件互连快速（PCIe）段来管理平台管理消息的方法。

5. 发明授权

US08930609B2 Method, apparatus, and system for manageability and secure routing and endpoint access 有权
标题翻译：用于可管理性和安全路由和端点访问的方法，设备和系统
公开(公告)号：US08930609B2
公开(公告)日：2015-01-06
申请号：US12806643
申请日：2010-08-18
申请人： Mahesh Natu , Eric J. Dahlen
发明人： Mahesh Natu , Eric J. Dahlen
IPC分类号： G06F13/36 , H04L29/06 , G06F13/40
CPC分类号： G06F21/85 , G06F13/4027 , G06F2221/2141 , H04L63/101 , H04L63/104 , H04L63/20
摘要： A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.
摘要翻译：提供了解决方案来保护端点，而不需要单独的总线或通信路径。该解决方案允许通过利用管理协议控制对端点的访问，通过与分组格式的现有互连通信路径重叠并利用PCI地址BDF（总线号码，设备号码和功能号码）进行验证。

6. 发明申请

US20140281070A1 Method and System for Platform Management Messages Across Peripheral Component Interconnect Express (PCIE) Segments 有权
标题翻译：跨平台管理消息的方法和系统跨PCI Express（PCIE）段
公开(公告)号：US20140281070A1
公开(公告)日：2014-09-18
申请号：US13843066
申请日：2013-03-15
申请人： Mahesh Natu , Mohan Nair
发明人： Mahesh Natu , Mohan Nair
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , G06F12/06
摘要： A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.
摘要翻译：公开了一种通过在计算系统的根复合体上实现的多个外围组件互连快速（PCIe）段来管理平台管理消息的方法。

7. 发明申请

US20140040543A1 Providing State Storage in a Processor for System Management Mode 审中-公开
标题翻译：在处理器中为系统管理模式提供状态存储
公开(公告)号：US20140040543A1
公开(公告)日：2014-02-06
申请号：US14048451
申请日：2013-10-08
申请人： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G11C7/10
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态管理模式（SMM）。以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。描述和要求保护其他实施例。

8. 发明申请

US20050071618A1 Method and apparatus to support legacy master boot record (MBR) partitions 失效
标题翻译：支持传统主引导记录（MBR）分区的方法和设备
公开(公告)号：US20050071618A1
公开(公告)日：2005-03-31
申请号：US10935956
申请日：2004-09-08
申请人： Mahesh Natu
发明人： Mahesh Natu
IPC分类号： G06F9/00 , G06F9/445 , G06F15/177
CPC分类号： G06F9/4411 , G06F9/4406
摘要： Disclosed is a method, apparatus, and system in which a basic input/output BIOS is run and a non-volatile memory coupled to the BIOS is read. The BIOS determines if legacy partition address data is not present for a disk partition identified in the non-volatile memory, and if legacy partition address data is not present for the disk partition, legacy partition address data may be obtained by a legacy OPROM. The disk drive may then be updated with the legacy partition address data.
摘要翻译：公开了一种方法，装置和系统，其中运行基本输入/输出BIOS并读取耦合到BIOS的非易失性存储器。 BIOS确定对于在非易失性存储器中标识的磁盘分区是否不存在传统分区地址数据，并且如果传统分区地址数据不存在于磁盘分区，则传统分区地址数据可以由传统OPROM获得。然后可以用传统分区地址数据来更新磁盘驱动器。

9. 发明授权

US5790850A Fault resilient booting for multiprocessor computer systems 失效
标题翻译：多处理器计算机系统的故障恢复启动
公开(公告)号：US5790850A
公开(公告)日：1998-08-04
申请号：US723909
申请日：1996-09-30
申请人： Mahesh Natu
发明人： Mahesh Natu
IPC分类号： G06F9/445 , G06F11/14 , G06F9/06
CPC分类号： G06F15/177 , G06F11/1417 , G06F9/4405
摘要： A multiprocessor computer system determines that the hard reset designated BSP has failed by examining its status bits. The designated BSP then selects a processor from among the APs that will take the place of the designated BSP. The selection is accomplished by, successively for every AP indicated to be good by examining its corresponding status flag, determining whether the AP is present, starting up the AP if it is present, determining whether the AP has passed its BIST, and selecting the AP to take the place of the designated BSP if the AP has passed its BIST. The BSP then designates the selected AP as the BSP instead of itself. The bootstrap indicator bit of the selected AP is set to indicate that the AP is the BSP. The bootstrap indicator bit of the designated BSP is cleared. The computer system then undergoes a soft reset which causes the selected AP to become the BSP and begin running the BIOS code from the reset vector.
摘要翻译：多处理器计算机系统通过检查其状态位来确定指定的BSP的硬复位失败。指定的BSP然后从将取代指定的BSP的AP中选择一个处理器。通过检查其对应的状态标志，确定AP是否存在，确定AP是否存在，启动AP，确定AP是否已经通过其BIST，并选择AP来进行选择取代指定的BSP，如果AP通过其BIST。 BSP然后将所选择的AP指定为BSP而不是其本身。所选AP的引导指示符位被设置为指示AP是BSP。指定BSP的自举指示符位清零。然后，计算机系统经历软复位，使得所选择的AP成为BSP，并从复位向量开始运行BIOS代码。

10. 发明申请

US20120047309A1 Method, apparatus, and system for manageability and secure routing and endpoint access 有权
标题翻译：用于可管理性和安全路由和端点访问的方法，设备和系统
公开(公告)号：US20120047309A1
公开(公告)日：2012-02-23
申请号：US12806643
申请日：2010-08-18
申请人： Mahesh Natu , Eric J. Dahlen
发明人： Mahesh Natu , Eric J. Dahlen
IPC分类号： G06F13/36
CPC分类号： G06F21/85 , G06F13/4027 , G06F2221/2141 , H04L63/101 , H04L63/104 , H04L63/20
摘要： A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.
摘要翻译：提供了解决方案来保护端点，而不需要单独的总线或通信路径。该解决方案允许通过利用管理协议控制对端点的访问，通过与分组格式的现有互连通信路径重叠并利用PCI地址BDF（总线号码，设备号码和功能号码）进行验证。

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