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    • 10. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US07123510B2
    • 2006-10-17
    • US11058374
    • 2005-02-16
    • Makoto KojimaTakafumi Maruyama
    • Makoto KojimaTakafumi Maruyama
    • G11C16/04
    • G11C16/04
    • A plurality of memory cells are connected between two adjacent sub-bit lines. A row decoder 3 selects a word line connected to a memory cell to be read. A selection line selection circuit 2 and a column selection circuit 5 include first and second selection portions that perform selection operations simultaneously and independently. The first selection portion selects a first pair of main bit lines and selection lines in order to select the memory cell to be read. The second selection portion selects a second pair of main bit lines that is different from the first pair of main bit lines and selection lines for selecting a sector different from that for the memory cell to be read in order to select a line to be used for reading a reference voltage.
    • 多个存储单元连接在两个相邻的子位线之间。 行解码器3选择连接到要读取的存储单元的字线。 选择线选择电路2和列选择电路5包括同时且独立地执行选择操作的第一和第二选择部分。 第一选择部分选择第一对主位线和选择线,以选择要读取的存储单元。 第二选择部分选择不同于第一对主位线和选择线的第二对主位线,用于选择与要读取的存储单元的扇区不同的扇区,以便选择要用于 读取参考电压。