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1. 发明授权

US07681107B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07681107B2
公开(公告)日：2010-03-16
申请号：US11045066
申请日：2005-01-31
申请人： Makoto Muranushi , Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Norihiro Ikeda
发明人： Makoto Muranushi , Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Norihiro Ikeda
IPC分类号： G11C29/00
CPC分类号： G11C29/021 , G11C5/141 , G11C29/028 , G11C29/52
摘要： A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.
摘要翻译：具有本发明的内部存储器的半导体包括第一存储器复制和保存保存在存储装置中的数据; 保持在第一存储器中的数据的校验码的第二存储器，并且不断地提供不低于数据保持电压的源电压; 数据检查单元，基于所述校验码检测由所述第一存储器保存的数据中的错误; 并且重新加载单元仅将与由数据检查单元检测到的具有数据错误的块相对应的数据从存储设备复制到第一存储器，以使得可以检测到在第一存储器中保存的数据中的任何错误，由此保证数据，并降低要提供给第一个存储器的源电压。

2. 发明申请

US20060095829A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060095829A1
公开(公告)日：2006-05-04
申请号：US11045066
申请日：2005-01-31
申请人： Makoto Muranushi , Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Norihiro Ikeda
发明人： Makoto Muranushi , Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Norihiro Ikeda
IPC分类号： G11C29/00
CPC分类号： G11C29/021 , G11C5/141 , G11C29/028 , G11C29/52
摘要： A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.
摘要翻译：具有本发明的内部存储器的半导体包括第一存储器复制和保存保存在存储装置中的数据; 保持在第一存储器中的数据的校验码的第二存储器，并且不断地提供不低于数据保持电压的源电压; 数据检查单元，基于所述校验码检测由所述第一存储器保持的数据中的错误; 并且重新加载单元仅将与由数据检查单元检测到的具有数据错误的块相对应的数据从存储设备复制到第一存储器，以使得可以检测到在第一存储器中保存的数据中的任何错误，由此保证数据，并降低要提供给第一个存储器的源电压。

3. 发明授权

US07260710B2 Initializing function block registers using value supplying setting interface coupled to table linking block identifier to multiple register address set 有权
标题翻译：初始化功能块寄存器，使用值提供设置界面，将表链接块标识符耦合到多个寄存器地址集
公开(公告)号：US07260710B2
公开(公告)日：2007-08-21
申请号：US11091584
申请日：2005-03-29
申请人： Koichi Kuroiwa , Norihiro Ikeda , Masami Kanasugi , Shoji Taniguchi
发明人： Koichi Kuroiwa , Norihiro Ikeda , Masami Kanasugi , Shoji Taniguchi
IPC分类号： G06F9/312
CPC分类号： G06F9/30138 , G06F9/30098 , G06F9/30101 , G06F9/384
摘要： A processor (1) having an instruction memory (2) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (3), and address values of the registers are outputted from an address output unit (5) based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.
摘要翻译：具有指令存储器（2）的处理器（1）将设置为寄存器（REGA至REGD）的寻址信息和设置值提供给设置接口单元（3），并且从地址输出单元输出寄存器的地址值（5）基于寻址信息。将输出的地址值和设定值分别输出到寄存器以设定设定值，使得处理器可以将设定值设定为寄存器而不意识到寄存器的地址，因此可以减少寻址指令代码中的各个寄存器的部分，并且减少指令代码的数量，这有助于指令代码的编码。

4. 发明申请

US20050210230A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050210230A1
公开(公告)日：2005-09-22
申请号：US11091584
申请日：2005-03-29
申请人： Koichi Kuroiwa , Norihiro Ikeda , Masami Kanasugi , Shoji Taniguchi
发明人： Koichi Kuroiwa , Norihiro Ikeda , Masami Kanasugi , Shoji Taniguchi
IPC分类号： G06F9/30 , G06F15/76 , G06F15/78
CPC分类号： G06F9/30138 , G06F9/30098 , G06F9/30101 , G06F9/384
摘要： A processor (1) having an instruction memory (2) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (3), and address values of the registers are outputted from an address output unit (5) based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.
摘要翻译：具有指令存储器（2）的处理器（1）将设置为寄存器（REGA至REGD）的寻址信息和设置值提供给设置接口单元（3），并且从地址输出单元输出寄存器的地址值（5）基于寻址信息。将输出的地址值和设定值分别输出到寄存器以设定设定值，使得处理器可以将设定值设定为寄存器而不意识到寄存器的地址，因此可以减少寻址指令代码中的各个寄存器的部分，并且减少指令代码的数量，这有助于指令代码的编码。

5. 发明授权

US06753795B2 Code generation device, semiconductor device, and receiver device 有权
标题翻译：代码生成装置，半导体装置和接收装置
公开(公告)号：US06753795B2
公开(公告)日：2004-06-22
申请号：US10342094
申请日：2003-01-15
申请人： Norihiro Ikeda , Shoji Taniguchi , Masami Kanasugi , Koichi Kuroiwa
发明人： Norihiro Ikeda , Shoji Taniguchi , Masami Kanasugi , Koichi Kuroiwa
IPC分类号： H03M700
CPC分类号： H04J13/10
摘要： In a code generation device for generating a code: a binary-data generation circuit generates first binary data items indicating every (m+1)th one of n successive binary numbers, where m≧1 and n≧2. A binary-data derivation circuit derives m+1 second binary data items indicating m+1 binary numbers from each of the first binary data items, where the m+1 binary numbers include the first binary data item. A first processing circuit performs a predetermined common operation on identical portions of the m+1 second binary data items, and a second processing circuit performs individually predetermined operations on non-identical portions of the m+1 second binary data items, where states of corresponding bits in the non-identical portions of the m+1 second binary data items are not identical. A combining circuit combines the outputs of the first and second processing circuits.
摘要翻译：在用于生成代码的代码生成装置中，二进制数据生成电路生成表示n个连续的二进制数的每个（m + 1）个的第二个二进制数据项，其中m≥1且n> = 2。二进制数据导出电路从每个第一二进制数据项导出指示m + 1个二进制数的m + 1秒二进制数据项，其中m + 1个二进制数包括第一个二进制数据项。第一处理电路对m + 1个第二二进制数据项的相同部分执行预定的公共操作，第二处理电路对m + 1个第二二进制数据项的不相同部分执行单独预定的操作，其中相应的 m + 1个第二二进制数据项的不相同部分中的位不相同。组合电路组合第一和第二处理电路的输出。

6. 发明授权

US07573779B2 Semiconductor memory and electronic device 有权
标题翻译：半导体存储器和电子器件
公开(公告)号：US07573779B2
公开(公告)日：2009-08-11
申请号：US12000051
申请日：2007-12-07
申请人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
发明人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/14
摘要： A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.
摘要翻译：一种半导体存储器，其在不进行微处理器控制的情况下降低存储单元阵列的功耗。半导体存储器包括存储单元阵列，用于接通/关断与存储单元阵列的行地址相对应的功率的开关，用于根据在第一时钟产生的写指针（WP）进行序列控制的地址控制部分，输入写入信号，用于指定要写入预定数据流的数据的行地址和在输入读取信号时生成的读取指针（RP），用于指定数据从该地址到的行地址读出，以及开关信号输出部，用于根据WP和RP产生用于控制开关的开关信号。

7. 发明申请

US20080130393A1 Semiconductor memory and electronic device 有权
标题翻译：半导体存储器和电子器件
公开(公告)号：US20080130393A1
公开(公告)日：2008-06-05
申请号：US12000051
申请日：2007-12-07
申请人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
发明人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
IPC分类号： G11C7/00 , G11C8/00 , G11C5/14
CPC分类号： G11C8/08 , G11C5/14
摘要： A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.
摘要翻译：一种半导体存储器，其在不进行微处理器控制的情况下降低存储单元阵列的功耗。半导体存储器包括存储单元阵列，用于接通/关断与存储单元阵列的行地址相对应的功率的开关，用于基于在第一时钟产生的写指针（WP）进行序列控制的地址控制部分，输入写入信号，用于指定要写入预定数据流的数据的行地址和在输入读取信号时生成的读取指针（RP），用于指定数据从该地址到的行地址读出，以及开关信号输出部，用于根据WP和RP产生用于控制开关的开关信号。

8. 发明授权

US08074096B2 Semiconductor integrated circuit, memory system, memory controller and memory control method 有权
标题翻译：半导体集成电路，存储器系统，存储器控制器和存储器控制方法
公开(公告)号：US08074096B2
公开(公告)日：2011-12-06
申请号：US12049551
申请日：2008-03-17
申请人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi , Koji Nozoe , Kunimitsu Itashiki
发明人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi , Koji Nozoe , Kunimitsu Itashiki
IPC分类号： G06F1/00 , G06F1/12 , G06F12/00
CPC分类号： G06F13/4243
摘要： Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.
摘要翻译：该实施例的方面提供一种半导体集成电路，其包括通过控制总线耦合到存储器的控制终端，通过数据总线耦合到存储器的数据终端，耦合到控制终端和数据终端的存储器控制器以及第一主控器以及耦合到所述存储器控制器的第二主机，其中所述存储器控制器基于所述第一主机将对应于存储器访问的控制信号和对应于基于所述第二主机的存储器访问的控制信号与控制终端同步地向控制终端提供时钟信号的上升沿和下降沿，并且存储器控制器与上升沿和下降沿同步地在数据端子处接收和输出第二主控器的第一主控器的输入/输出数据和输入/输出数据边缘。

9. 发明授权

US07032161B2 Error detector, semiconductor device, and error detection method 有权
公开(公告)号：US07032161B2
公开(公告)日：2006-04-18
申请号：US10223216
申请日：2002-08-20
申请人： Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Mahiro Hikita
发明人： Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Mahiro Hikita
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

10. 发明授权

US06493844B1 Error detector, semiconductor device, and error detection method 有权
标题翻译：误差检测器，半导体器件和误差检测方法
公开(公告)号：US06493844B1
公开(公告)日：2002-12-10
申请号：US09311722
申请日：1999-05-14
申请人： Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Mahiro Hikita
发明人： Masami Kanasugi , Shoji Taniguchi , Koichi Kuroiwa , Mahiro Hikita
IPC分类号： H03M1300
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string generated at the transmitter so that errors in the reception bit string are detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
摘要翻译：接收机的误差检测器包括反馈移位寄存器。反馈移位寄存器中的移位方向与通过使用指定的生成多项式生成传输位串时的发送器处的移位方向相反。接收比特串以相反的顺序被输入到反馈移位寄存器，以便在发送器处产生的发送比特串，从而通过获得余数来检测接收比特串中的错误。接收机处的另一个误差检测器包括第一和第二反馈移位寄存器。第一和第二反馈移位寄存器中的相应移位方向与发送器在生成传输位串时的移位方向相同且相反。接收比特串以与生成发送比特串相同的顺序输入到第一反馈移位寄存器，而接收比特串以相反的顺序被输入到第二反馈移位寄存器，以产生发送比特串。通过比较由第一和第二反馈移位寄存器获得的各个余数来检测接收位串中的错误。这减少了错误检测所需的处理时间，并提高了检测传输数据中错误的效率。

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