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1. 发明授权

US08904156B2 Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor 有权
标题翻译：基于感知器的分支预测机制，用于在多线程处理器上预测条件分支指令
公开(公告)号：US08904156B2
公开(公告)日：2014-12-02
申请号：US12578859
申请日：2009-10-14
申请人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
发明人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3851
摘要： A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information.
摘要翻译：多线程微处理器包括指令提取单元，其包括基于感知器的条件分支预测单元，被配置为针对一个或多个并行执行的线程中的每一个为方向分支预测提供。条件分支预测单元包括多个存储器，每个存储器包括多个条目。每个条目可被配置为存储一个或多个预测值。给定存储器的每个预测值可以对应于高速缓存行中的至少一个条件转移指令。条件分支预测单元可以通过生成用于访问第一存储器的第一索引值来生成用于访问每个存储器的单独索引值，该第一索引值通过组合接收到的指令获取地址的一个或多个部分，并且生成彼此用于访问其他存储器的索引值通过将第一索引值与方向分支历史信息的不同部分组合。

2. 发明申请

US20110087866A1 PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITIONAL BRANCH INSTRUCTIONS ON A MULTITHREADED PROCESSOR 有权
标题翻译：基于PERCEPTRON的分支预测机制，用于预测多处理器上的条件分支指令
公开(公告)号：US20110087866A1
公开(公告)日：2011-04-14
申请号：US12578859
申请日：2009-10-14
申请人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
发明人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3851
摘要： A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information.
摘要翻译：多线程微处理器包括指令提取单元，其包括基于感知器的条件分支预测单元，被配置为针对一个或多个同时执行的线程中的每一个提供方向分支预测。条件分支预测单元包括多个存储器，每个存储器包括多个条目。每个条目可被配置为存储一个或多个预测值。给定存储器的每个预测值可以对应于高速缓存行中的至少一个条件转移指令。条件分支预测单元可以通过生成用于访问第一存储器的第一索引值来生成用于访问每个存储器的单独索引值，该第一索引值通过组合接收到的指令获取地址的一个或多个部分，并且生成彼此用于访问其他存储器的索引值通过将第一索引值与方向分支历史信息的不同部分组合。

3. 发明授权

US10346173B2 Multi-threaded instruction buffer design 有权
公开(公告)号：US10346173B2
公开(公告)日：2019-07-09
申请号：US13041881
申请日：2011-03-07
申请人： Jama I. Barreh , Robert T. Golla , Manish K. Shah
发明人： Jama I. Barreh , Robert T. Golla , Manish K. Shah
IPC分类号： G06F9/30 , G06F9/38
摘要： An instruction buffer for a processor configured to execute multiple threads is disclosed. The instruction buffer is configured to receive instructions from a fetch unit and provide instructions to a selection unit. The instruction buffer includes one or more memory arrays comprising a plurality of entries configured to store instructions and/or other information (e.g., program counter addresses). One or more indicators are maintained by the processor and correspond to the plurality of threads. The one or more indicators are usable such that for instructions received by the instruction buffer, one or more of the plurality entries of a memory array can be determined as a write destination for the received instructions, and for instructions to be read from the instruction buffer (and sent to a selection unit), one or more entries can be determined as the correct source location from which to read.

4. 发明申请

US20120233441A1 MULTI-THREADED INSTRUCTION BUFFER DESIGN 审中-公开
标题翻译：多线程指令缓冲区设计
公开(公告)号：US20120233441A1
公开(公告)日：2012-09-13
申请号：US13041881
申请日：2011-03-07
申请人： Jama I. Barreh , Robert T. Golla , Manish K. Shah
发明人： Jama I. Barreh , Robert T. Golla , Manish K. Shah
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3814
摘要： An instruction buffer for a processor configured to execute multiple threads is disclosed. The instruction buffer is configured to receive instructions from a fetch unit and provide instructions to a selection unit. The instruction buffer includes one or more memory arrays comprising a plurality of entries configured to store instructions and/or other information (e.g., program counter addresses). One or more indicators are maintained by the processor and correspond to the plurality of threads. The one or more indicators are usable such that for instructions received by the instruction buffer, one or more of the plurality entries of a memory array can be determined as a write destination for the received instructions, and for instructions to be read from the instruction buffer (and sent to a selection unit), one or more entries can be determined as the correct source location from which to read.
摘要翻译：公开了一种用于执行多个线程的处理器的指令缓冲器。指令缓冲器被配置为从获取单元接收指令并向选择单元提供指令。指令缓冲器包括一个或多个存储器阵列，其包括被配置为存储指令和/或其他信息（例如，程序计数器地址）的多个条目。一个或多个指示器由处理器维护并对应于多个线程。一个或多个指示符是可用的，使得对于由指令缓冲器接收的指令，可以将存储器阵列的多个条目中的一个或多个确定为所接收指令的写目的地，并且从指令缓冲器读取指令（并发送到选择单元），可以将一个或多个条目确定为要从其读取的正确的源位置。

5. 发明授权

US07434000B1 Handling duplicate cache misses in a multithreaded/multi-core processor 有权
标题翻译：处理多线程/多核处理器中的重复高速缓存未命中
公开(公告)号：US07434000B1
公开(公告)日：2008-10-07
申请号：US11008016
申请日：2004-12-09
申请人： Jama I. Barreh , Manish K. Shah
发明人： Jama I. Barreh , Manish K. Shah
IPC分类号： G06F12/00 , G06F9/46
CPC分类号： G06F12/0859 , G06F12/0842
摘要： In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor. Furthermore, the cache miss unit is configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line. The cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss.
摘要翻译：在一个实施例中，处理器包括耦合到高速缓存的高速缓存和高速缓存未命中单元。高速缓存未命中单元被配置为响应于高速缓存中的第一高速缓存未命中而发起用于缓存的高速缓存线的高速缓冲存储器填充，其中第一高速缓存未命中对应于由处理器执行的多个线程的第一线程。此外，高速缓存未命中单元被配置为记录与多个线程中的第二线程相对应的附加高速缓存未命中，其中在高速缓存填满完成高速缓存线之前，高速缓存未命中出现在高速缓存中。高速缓存未命中单元被配置为响应于额外的高速缓存未命中而禁止启动额外的高速缓存填充。

6. 发明授权

US07353445B1 Cache error handling in a multithreaded/multi-core processor 有权
标题翻译：多线程/多核处理器中的缓存错误处理
公开(公告)号：US07353445B1
公开(公告)日：2008-04-01
申请号：US11009244
申请日：2004-12-10
申请人： Jama I. Barreh , Manish K. Shah
发明人： Jama I. Barreh , Manish K. Shah
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of a plurality of threads. Coupled to receive an indication of the error, the fetch control unit is configured to inhibit fetching for the first thread responsive to the error until the thread is redirected in response to the error and until the error is eliminated from the cache that includes the data.
摘要翻译：在一个实施例中，处理器包括由处理器执行的多个线程共享的高速缓存器，耦合到高速缓存的错误检测单元以及获取控制单元。错误检测单元被配置为响应于对应于多个线程的第一线程的访问来检测由高速缓存输出的数据中的错误。为了接收到错误的指示，获取控制单元被配置为响应于错误禁止针对第一线程的提取，直到响应于错误重定向线程，直到从包括数据的高速缓存中消除错误为止。

7. 发明授权

US08429386B2 Dynamic tag allocation in a multithreaded out-of-order processor 有权
标题翻译：多线程无序处理器中的动态标签分配
公开(公告)号：US08429386B2
公开(公告)日：2013-04-23
申请号：US12494532
申请日：2009-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
摘要翻译：公开了用于动态分配指令标签和使用这些标签的各种技术。这些技术可能适用于支持无序执行的处理器和支持多线程的体系结构。可以从可用标签值池中分配一组指令。标签值可用于确定相对于线程中的其他指令的一组指令的程序顺序。在指示组（或将要））提交之后，可以释放标签值，以便可以在第二组指令上重新使用。标记值在线程之间动态分配; 因此，特定标签值或标签值的范围不专用于特定线程。

8. 发明申请

US20100274961A1 PHYSICALLY-INDEXED LOGICAL MAP TABLE 审中-公开
标题翻译：物理索引逻辑映射表
公开(公告)号：US20100274961A1
公开(公告)日：2010-10-28
申请号：US12428457
申请日：2009-04-22
申请人： Robert T. Golla , Jama I. Barreh , Howard L. Levy
发明人： Robert T. Golla , Jama I. Barreh , Howard L. Levy
IPC分类号： G06F12/10 , G06F12/02 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/30112 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3877
摘要： Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments.
摘要翻译：这里描述了技术和系统以维持逻辑到物理寄存器的映射，例如在支持重命名的多线程处理器的上下文中。映射单元可以具有多个条目，每个条目存储用于处理器可用于重命名的一组物理寄存器中的专用的一个的重命名信息。该物理索引映射单元可以支持多个线程，并且在某些实施例中可以包括内容寻址存储器（CAM）。映射单元可以支持读取操作的各种组合（以确定逻辑寄存器是否映射到物理寄存器），写入操作（用于创建或修改包含映射信息的一个或多个条目），线程刷新操作和提交操作。在某些实施例中，可以基本上同时执行多于一个这样的操作。

9. 发明授权

US09529594B2 Miss buffer for a multi-threaded processor 有权
标题翻译：一个多线程处理器的缓冲区
公开(公告)号：US09529594B2
公开(公告)日：2016-12-27
申请号：US12956409
申请日：2010-11-30
申请人： Manish K. Shah , Jama I. Barreh
发明人： Manish K. Shah , Jama I. Barreh
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/3851 , G06F9/5027
摘要： A multi-threaded processor configured to allocate entries in a buffer for instruction cache misses is disclosed. Entries in the buffer may store thread state information for a corresponding instruction cache miss for one of a plurality of threads executable by the processor. The buffer may include dedicated entries and dynamically allocable entries, where the dedicated entries are reserved for a subset of the plurality of threads and the dynamically allocable entries are allocable to a group of two or more of the plurality of threads. In one embodiment, the dedicated entries are dedicated for use by a single thread and the dynamically allocable entries are allocable to any of the plurality of threads. The buffer may store two or more entries for a given thread at a given time. In some embodiments, the buffer may help ensure none of the plurality of threads experiences starvation with respect to instruction fetches.
摘要翻译：公开了一种被配置为在缓冲器中分配用于指令高速缓存未命中的条目的多线程处理器。缓冲器中的条目可以存储针对可由处理器执行的多个线程中的一个的相应指令高速缓存未命中的线程状态信息。缓冲器可以包括专用条目和动态可分配条目，其中为多个线程的子集保留专用条目，并且动态可分配条目可分配给多个线程中的两个或多个线程的一组。在一个实施例中，专用条目专用于单个线程使用，并且动态可分配条目可分配给多个线程中的任何一个。缓冲区可以在给定的时间为给定的线程存储两个或多个条目。在一些实施例中，缓冲器可以帮助确保多个线程中的任何线程相对于指令提取都不经历饥饿。

10. 发明申请

US20130138888A1 STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN INSTRUCTION FIELD 审中-公开
标题翻译：在指挥领域存储控制传输指令的目标地址
公开(公告)号：US20130138888A1
公开(公告)日：2013-05-30
申请号：US13307850
申请日：2011-11-30
申请人： Jama I. Barreh , Manish K. Shah , Christopher H. Olson
发明人： Jama I. Barreh , Manish K. Shah , Christopher H. Olson
IPC分类号： G06F12/08
CPC分类号： G06F9/324 , G06F9/382 , G06F12/0862 , Y02D10/13
摘要： A control transfer instruction (CTI), such as a branch, jump, etc., may have an offset value for a control transfer that is to be performed. The offset value may be usable to compute a target address for the CTI (e.g., the address of a next instruction to be executed for a thread or instruction stream). The offset may be specified relative to a program counter. In response to detecting a specified offset value, the CTI may be modified to include at least a portion of a computed target address. Information indicating this modification has been performed may be stored, for example, in a pre-decode bit. In some cases, CTI modification may be performed only when a target address is a “near” target, rather than a “far” target. Modifying CTIs as described herein may eliminate redundant address calculations and produce a savings of power and/or time in some embodiments.
摘要翻译：诸如分支，跳转等的控制传送指令（CTI）可以具有要执行的控制传输的偏移值。偏移值可用于计算CTI的目标地址（例如，针对线程或指令流执行的下一条指令的地址）。可以相对于程序计数器指定偏移量。响应于检测到指定的偏移值，可以修改CTI以包括计算的目标地址的至少一部分。已经执行了表示该修改的信息可以被存储在例如预解码位中。在某些情况下，仅当目标地址是“近”目标而不是“远”目标时才可以执行CTI修改。如本文所述的修改CTI可以在一些实施例中消除冗余地址计算并产生功率和/或时间的节省。

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