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1. 发明授权

US08314448B2 Transistors with immersed contacts 有权
标题翻译：具有浸没触点的晶体管
公开(公告)号：US08314448B2
公开(公告)日：2012-11-20
申请号：US13105484
申请日：2011-05-11
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L29/80
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
摘要翻译：半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。

2. 发明授权

US07723805B2 Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权
标题翻译：包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺
公开(公告)号：US07723805B2
公开(公告)日：2010-05-25
申请号：US11328594
申请日：2006-01-10
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。在一个实施例中，电源电压低于通道区域的相对较高的VT。还公开了一种用于形成电子器件的工艺。

3. 发明申请

US20110210395A1 TRANSISTORS WITH IMMERSED CONTACTS 有权
标题翻译：具有不连续接触的晶体管
公开(公告)号：US20110210395A1
公开(公告)日：2011-09-01
申请号：US13105484
申请日：2011-05-11
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
摘要翻译：半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。

4. 发明授权

US07986006B2 Single transistor memory cell with reduced recombination rates 有权
标题翻译：具有降低复合率的单晶体管存储单元
公开(公告)号：US07986006B2
公开(公告)日：2011-07-26
申请号：US12398387
申请日：2009-03-05
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/331
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/7841 , H01L29/78687
摘要： A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
摘要翻译：半导体制造方法包括形成半导体结构，该半导体结构包括设置在沟道体两侧的源极/漏极区，其中源极/漏极区包括第一半导体材料，并且其中沟道主体包括第二半导体材料的迁移势垒。栅极电介质覆盖半导体结构，并且栅极模块覆盖在栅极电介质上。在第一和第二半导体材料之间的多数载流子势能级中的偏移对于通道体中的多数载流子产生潜在的井。迁移障碍物可以是第一半导体材料的第一层上的第二半导体材料层和第一半导体材料的覆盖层之下的层。在一维迁移屏障中，迁移屏障横向延伸穿过源极/漏极区域，而在二维屏障中，屏障在由栅极模块限定的边界处横向终止。

5. 发明授权

US07105430B2 Method for forming a semiconductor device having a notched control electrode and structure thereof 有权
标题翻译：用于形成具有切口控制电极的半导体器件及其结构的方法
公开(公告)号：US07105430B2
公开(公告)日：2006-09-12
申请号：US10811461
申请日：2004-03-26
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/3205
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28114
摘要： A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the-insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).
摘要翻译：一种形成半导体器件（10）的方法包括提供具有表面的衬底（20）; 在所述衬底（20）的表面上形成绝缘层（22）; 在所述绝缘层（22）上形成第一图案化导电层（30）; 在所述第一图案化导电层（30）上形成第二图案化导电层（32）; 在所述第二图案化导电层（32）上形成图案化的非绝缘层（34）; 以及选择性地去除所述第一和第二图案化导电层（30,32）的部分以形成用于所述半导体器件（10）的切口控制电极。

6. 发明授权

US07968394B2 Transistor with immersed contacts and methods of forming thereof 有权
标题翻译：具有浸入触点的晶体管及其形成方法
公开(公告)号：US07968394B2
公开(公告)日：2011-06-28
申请号：US11311587
申请日：2005-12-16
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure of the semiconductor structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. The method further includes forming a first contact, wherein forming the first contact includes removing a first portion of the semiconductor structure to form an opening, wherein the opening is in the first current electrode region and forming contact material in the opening.
摘要翻译：一种包括形成半导体结构的方法，所述半导体结构包括第一电流电极区域，第二电流电极区域和沟道区域，所述沟道区域位于所述第一电流电极区域和所述第二电流电极区域之间，其中所述沟道区域位于半导体结构的翅片结构中，其中通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。所述方法还包括形成第一接触，其中形成所述第一接触包括移除所述半导体结构的第一部分以形成开口，其中所述开口位于所述第一电流电极区域中并在所述开口中形成接触材料。

7. 发明授权

US07939412B2 Process for forming an electronic device including a fin-type transistor structure 有权
标题翻译：用于形成包括鳍型晶体管结构的电子器件的工艺
公开(公告)号：US07939412B2
公开(公告)日：2011-05-10
申请号：US12753226
申请日：2010-04-02
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅极电极之间。半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。在一个实施例中，电源电压低于通道区域的相对较高的VT。还公开了一种用于形成电子器件的工艺。

8. 发明授权

US08633515B2 Transistors with immersed contacts 有权
标题翻译：具有浸没触点的晶体管
公开(公告)号：US08633515B2
公开(公告)日：2014-01-21
申请号：US13613614
申请日：2012-09-13
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. A contact extends into the first current electrode region and is electrically coupled to the first current electrode region.
摘要翻译：半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。触点延伸到第一电流电极区域中并且电耦合到第一电流电极区域。

9. 发明申请

US20100190308A1 ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括FIN型晶体管结构的电子器件和形成电子器件的工艺
公开(公告)号：US20100190308A1
公开(公告)日：2010-07-29
申请号：US12753226
申请日：2010-04-02
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。在一个实施例中，电源电压低于通道区域的相对较高的VT。还公开了一种用于形成电子器件的工艺。

10. 发明授权

US07517741B2 Single transistor memory cell with reduced recombination rates 失效
标题翻译：具有降低复合率的单晶体管存储单元
公开(公告)号：US07517741B2
公开(公告)日：2009-04-14
申请号：US11172569
申请日：2005-06-30
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/7841 , H01L29/78687
摘要： A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
摘要翻译：半导体制造方法包括形成半导体结构，该半导体结构包括设置在沟道体两侧的源极/漏极区，其中源极/漏极区包括第一半导体材料，并且其中沟道主体包括第二半导体材料的迁移势垒。栅极电介质覆盖半导体结构，并且栅极模块覆盖在栅极电介质上。在第一和第二半导体材料之间的多数载流子势能级中的偏移对于通道体中的多数载流子产生潜在的井。迁移障碍物可以是第一半导体材料的第一层上的第二半导体材料层和第一半导体材料的覆盖层之下的层。在一维迁移屏障中，迁移屏障横向延伸穿过源极/漏极区域，而在二维屏障中，屏障在由栅极模块限定的边界处横向终止。

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