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1. 发明授权

US11037923B2 Through gate fin isolation 有权
公开(公告)号：US11037923B2
公开(公告)日：2021-06-15
申请号：US13538935
申请日：2012-06-29
申请人： Mark T. Bohr , Stephen M. Cea , Barbara A. Chappell
发明人： Mark T. Bohr , Stephen M. Cea , Barbara A. Chappell
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L21/84
摘要： Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

2. 发明申请

US20140001572A1 THROUGH GATE FIN ISOLATION 审中-公开
标题翻译：通过门盖隔离
公开(公告)号：US20140001572A1
公开(公告)日：2014-01-02
申请号：US13538935
申请日：2012-06-29
申请人： Mark T. BOHR , Stephen M. Cea , Barbara A. Chappell
发明人： Mark T. BOHR , Stephen M. Cea , Barbara A. Chappell
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.
摘要翻译：通过诸如集成电路（IC）的微电子器件中的非平面晶体管的栅极鳍隔离。在实施例中，相邻半导体鳍片的端部通过与半导体鳍片的栅电极自对准的隔离区域彼此电绝缘，从而能够实现更高的晶体管封装密度和其他益处。在一个实施例中，使用单个掩模来形成固定间距的多个牺牲占位符条，去除占位符条的第一子集，并且在由第一子集移除产生的开口中形成到半导体鳍片中的隔离切割，而第二子集的占位符条纹被栅电极所取代。

3. 发明授权

US06556471B2 VDD modulated SRAM for highly scaled, high performance cache 有权
标题翻译： VDD调制SRAM用于高度缩放，高性能的缓存
公开(公告)号：US06556471B2
公开(公告)日：2003-04-29
申请号：US09893236
申请日：2001-06-27
申请人： Barbara A. Chappell , Ian Young
发明人： Barbara A. Chappell , Ian Young
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.
摘要翻译：本发明提供一种用于快速SRAM读写的装置和方法。提供升压电压源，其中升压电压源操作以相对于SRAM单元中的存取器件的电导增加SRAM单元中的锁存器件的电导。由于锁存器和存取器件之间的相对电导率增加（β比率），存取器件可以采取更宽的宽度，而不会危及电池的读取稳定性。

4. 发明授权

US5942917A High speed ratioed CMOS logic structures for a pulsed input environment 失效
标题翻译：用于脉冲输入环境的高速比CMOS逻辑结构
公开(公告)号：US5942917A
公开(公告)日：1999-08-24
申请号：US999102
申请日：1997-12-29
申请人： Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
发明人： Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
IPC分类号： H03K19/20 , H03K19/0948 , H03K19/096 , H03K19/094
CPC分类号： H03K19/0963 , H03K19/0948
摘要： A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.
摘要翻译：适于接收脉冲有源输入信号的逻辑结构产生具有非常小的固有切换延迟的逻辑输出。比较下拉晶体管和互补上拉晶体管，使得默认逻辑输出电平保持接近标称值，即使当逻辑结构吸收或输出直流电流时。当脉冲输入信号无效时，不启用直流电流路径。

5. 发明授权

US5204841A Virtual multi-port RAM 失效
标题翻译：虚拟多端口RAM
公开(公告)号：US5204841A
公开(公告)日：1993-04-20
申请号：US873672
申请日：1992-04-23
申请人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
IPC分类号： G06F12/04 , G06F12/08 , G11C7/10 , G11C8/12 , G11C8/16
CPC分类号： G11C8/16 , G06F12/04 , G11C7/103 , G11C8/12 , G06F12/0855
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译：虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。

6. 发明授权

US4697108A Complementary input circuit with nonlinear front end and partially coupled latch 失效
标题翻译：具有非线性前端和部分耦合锁存器的互补输入电路
公开(公告)号：US4697108A
公开(公告)日：1987-09-29
申请号：US861166
申请日：1986-05-09
申请人： Barbara A. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Stanley E. Schuster
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/003 , H03K19/0175 , H03K19/096
CPC分类号： H03K3/356113 , H03K3/356017
摘要： A complementary input circuit with a nonlinear front end is used to transfer the state of an external input to the internal signal lines of an intetraged circuit chip such as a dynamic or static RAM. The combination of a nonlinear front end and a "partially" cross-coupled complementary latch provide good level detection.
摘要翻译：使用具有非线性前端的互补输入电路将外部输入的状态传送到诸如动态或静态RAM的内埋电路芯片的内部信号线。非线性前端和“部分”交叉耦合互补闩锁的组合提供了良好的电平检测。

7. 发明授权

US4845677A Pipelined memory chip structure having improved cycle time 失效
标题翻译：流水线存储芯片结构具有改进的周期时间
公开(公告)号：US4845677A
公开(公告)日：1989-07-04
申请号：US86136
申请日：1987-08-17
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C8/12 , G11C11/401 , G11C11/413
CPC分类号： G11C8/12 , G11C7/1039 , G11C7/12
摘要： A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

8. 发明授权

US4843261A Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories 失效
标题翻译：半导体存储器的互补输出，高密度CMOS解码器/驱动电路
公开(公告)号：US4843261A
公开(公告)日：1989-06-27
申请号：US161813
申请日：1988-02-29
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/413 , G11C8/10 , G11C11/408
CPC分类号： G11C8/10
摘要： A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .phi.PC line is included for receiving a .phi.PC precharge clock signal thereon and a .phi.R line is provided for receiving a .phi.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

9. 发明授权

US4533940A High spatial resolution energy discriminator 失效
标题翻译：高空间分辨率能量鉴别器
公开(公告)号：US4533940A
公开(公告)日：1985-08-06
申请号：US503945
申请日：1983-06-13
申请人： Barbara A. Chappell , Terry I. Chappell , Jerry M. Woodall
发明人： Barbara A. Chappell , Terry I. Chappell , Jerry M. Woodall
IPC分类号： H04N5/30 , H01J29/45 , H01L27/14 , H01L27/146 , H04N9/04
CPC分类号： H01L27/14647 , H01J29/45
摘要： An energy discriminator is provided wherein energy, entering through a receiving surface into a multilayer semiconductor monocrystalline body is converted into hole-electron pair carriers in different particular energy responsive layers and the electrons thereof are collected in potential wells that are asymmetric to electron flow associated with the particular layer.
摘要翻译：提供了一种能量鉴别器，其中通过接收表面进入多层半导体单晶体的能量被转换成不同特定能量响应层中的空穴 - 电子对载流子，并且其电子被收集在与电子流不对称的势阱中特定层。

10. 发明授权

US5541427A SRAM cell with capacitor 失效
标题翻译：带电容器的SRAM单元
公开(公告)号：US5541427A
公开(公告)日：1996-07-30
申请号：US162588
申请日：1993-12-03
申请人： Barbara A. Chappell , Bijan Davari , George A. Sai-Halasz , Yuan Taur
发明人： Barbara A. Chappell , Bijan Davari , George A. Sai-Halasz , Yuan Taur
IPC分类号： G11C11/412 , H01L27/11 , H01L27/108
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.
摘要翻译：存储锁存器，包括在所述衬底上的栅极绝缘层，穿过所述绝缘层形成的浅沟槽和所述衬底中的沟槽以提供器件绝缘; 以及在浅沟槽之间的衬底中的掺杂区域。掺杂区域定义源和漏极。栅极堆叠形成在与掺杂区域相邻的氧化物区域上。在栅极堆叠之间形成平坦化的绝缘体。在平坦化的绝缘体中提供了开口，用于与掺杂区域和栅极叠层的接触。导电材料填充开口以形成用于掺杂区域和栅极叠层的触点。平坦化绝缘体上的图案化的导电材料层连接用于闩锁的布线部分的所述触点中的所选择的一个。六器件SRAM单元包括形成在衬底中的深隔离沟槽; 第一锁存器，包括在所述沟槽的第一侧上由p型材料形成的两个晶体管; 包括在与沟槽的第一侧相对的沟槽的第二侧上由n型材料形成的两个晶体管的第二锁存器以及用于将第一锁存器的晶体管与第二锁存器的晶体管电交叉布线的连接装置。在形成锁存器时，使用用于单独形成与半导体衬底上的扩散区域和栅极堆叠的接触的自对准工艺。

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