专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10720517B2 Horizontal current bipolar transistor with floating field regions 有权
公开(公告)号：US10720517B2
公开(公告)日：2020-07-21
申请号：US16162643
申请日：2018-10-17
申请人： Marko Koricic , Tomislav Suligoj
发明人： Marko Koricic , Tomislav Suligoj
IPC分类号： H01L29/735 , H01L29/737 , H01L27/082 , H01L29/10 , H01L27/06 , H01L29/40 , H01L21/8249
摘要： A horizontal current bipolar transistor comprises; an n-hill layer on a substrate, forming a first pn-junction with the substrate; a n+ diffusion layer on the substrate, adjacent to the n-hill layer, forming a n+n junction with the n-hill layer; an intrinsic base layer on the n-hill layer and comprising a portion of a sidewall inclined at an acute angle to the substrate plane, forming a second pn-junction with the n-hill layer; an extrinsic base layer on the n-hill layer, forming a third pn-junction with the n-hill layer, and a p+p junction with the intrinsic base layer; a field limiting region on the n-hill layer, forming a fourth pn-junction with the n-hill layer. The field limiting region is spatially separated from the extrinsic base layer and the n+ diffusion layer. The extrinsic base layer and the field limiting region exhibit substantially equal impurity dopant distribution decay towards the substrate.

2. 发明申请

US20170179220A1 Horizontal Current Bipolar Transistors with Improved Breakdown Voltages 有权
公开(公告)号：US20170179220A1
公开(公告)日：2017-06-22
申请号：US14976461
申请日：2015-12-21
申请人： Marko Koricic , Tomislav Suligoj
发明人： Marko Koricic , Tomislav Suligoj
IPC分类号： H01L29/06 , H01L29/735 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/063 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/0808 , H01L29/1008 , H01L29/735
摘要： A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

3. 发明授权

US08569866B2 Hybrid-integrated lateral bipolar transistor and CMOS transistor and method for manufacturing the same 有权
标题翻译：混合集成横向双极晶体管和CMOS晶体管及其制造方法
公开(公告)号：US08569866B2
公开(公告)日：2013-10-29
申请号：US12808874
申请日：2008-12-19
申请人： Tomislav Suligoj , Marko Koricic , Hidenori Mochizuki , Soichi Morita
发明人： Tomislav Suligoj , Marko Koricic , Hidenori Mochizuki , Soichi Morita
IPC分类号： H01L21/331
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
摘要翻译：提供了适用于高性能横向晶体管（HCBT）和CMOS晶体管的混合集成（BiCMOS）的横向晶体管的结构以及制造横向晶体管的方法。半导体器件包括混合集成在其中的HCBT 100和CMOS晶体管200。 HCBT 100具有通过蚀刻围绕n-hill层11的器件隔离氧化膜6，发射电极31A和集电极31B而开放的开放区域21，其分别形成在开放区域21中，并且由多晶硅具有通过蚀刻器件隔离氧化膜而暴露的n-hill层11的厚度的膜和覆盖n-hill层11的至少一部分的超薄氧化膜24.超薄氧化膜24用作当蚀刻多晶硅膜以形成发射电极31A和集电极31B时，用于保护n-hill层11的保护膜不被蚀刻。

4. 发明授权

US09842834B2 Horizontal current bipolar transistors with improved breakdown voltages 有权
公开(公告)号：US09842834B2
公开(公告)日：2017-12-12
申请号：US14976461
申请日：2015-12-21
申请人： Marko Koricic , Tomislav Suligoj
发明人： Marko Koricic , Tomislav Suligoj
IPC分类号： H01L21/8248 , H01L27/06 , H01L29/06 , H01L29/735
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/063 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/0808 , H01L29/1008 , H01L29/735
摘要： A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

5. 发明申请

US20190115456A1 Horizontal Current Bipolar Transistor with Floating Field Regions 审中-公开
公开(公告)号：US20190115456A1
公开(公告)日：2019-04-18
申请号：US16162643
申请日：2018-10-17
申请人： Marko Koricic , Tomislav Suligoj
发明人： Marko Koricic , Tomislav Suligoj
IPC分类号： H01L29/735 , H01L29/737 , H01L29/10 , H01L27/082
摘要： A horizontal current bipolar transistor comprises; an n-hill layer on a substrate, forming a first pn-junction with the substrate; a n+ diffusion layer on the substrate, adjacent to the n-hill layer, forming a n+n junction with the n-hill layer; an intrinsic base layer on the n-hill layer and comprising a portion of a sidewall inclined at an acute angle to the substrate plane, forming a second pn-junction with the n-hill layer; an extrinsic base layer on the n-hill layer, forming a third pn-junction with the n-hill layer, and a p+p junction with the intrinsic base layer; a field limiting region on the n-hill layer, forming a fourth pn-junction with the n-hill layer. The field limiting region is spatially separated from the extrinsic base layer and the n+ diffusion layer. The extrinsic base layer and the field limiting region exhibit substantially equal impurity dopant distribution decay towards the substrate.

6. 发明申请

US20110266630A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110266630A1
公开(公告)日：2011-11-03
申请号：US12808874
申请日：2008-12-19
申请人： Tomislav Suligoj , Marko Koricic , Hidenori Mochizuki , Soichi Morita
发明人： Tomislav Suligoj , Marko Koricic , Hidenori Mochizuki , Soichi Morita
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
摘要翻译：提供了适用于高性能横向晶体管（HCBT）和CMOS晶体管的混合集成（BiCMOS）的横向晶体管的结构以及制造横向晶体管的方法。半导体器件包括混合集成在其中的HCBT 100和CMOS晶体管200。 HCBT 100具有通过蚀刻围绕n-hill层11的器件隔离氧化膜6，发射电极31A和集电极31B而开放的开放区域21，其分别形成在开放区域21中，并且由多晶硅具有通过蚀刻器件隔离氧化膜而暴露的n-hill层11的厚度的膜和覆盖n-hill层11的至少一部分的超薄氧化膜24.超薄氧化膜24用作当蚀刻多晶硅膜以形成发射电极31A和集电极31B时，用于保护n-hill层11的保护膜不被蚀刻。

7. 发明授权

US07038249B2 Horizontal current bipolar transistor and fabrication method 失效
标题翻译：水平电流双极晶体管及其制作方法
公开(公告)号：US07038249B2
公开(公告)日：2006-05-02
申请号：US10677643
申请日：2003-10-01
申请人： Tomislav Suligoj , Petar Biljanovic , Kang L. Wang
发明人： Tomislav Suligoj , Petar Biljanovic , Kang L. Wang
IPC分类号： H01L31/0328
CPC分类号： H01L29/6625 , H01L29/1008 , H01L29/735
摘要： A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.
摘要翻译：用于集成电路的双极晶体管结构，其中有源器件在n-hill的侧壁上被处理，使得表面覆盖区不依赖于有源器件区域（发射极区域）的期望区域。被称为水平电流双极晶体管（HCBT）的结构比常规器件消耗更小的芯片表面积，从而实现器件的更高的封装密度和/或集成电路管芯尺寸的降低。该器件采用单个多晶硅层制造，无需外延工艺，无需苛刻的沟槽隔离技术，并具有降低的热预算。与常规设备相比，制造需要更少的蚀刻工艺和热氧化。

8. 发明申请

US20190027527A1 Avalanche photodiode detector array with a crosstalk reduction layer 审中-公开
公开(公告)号：US20190027527A1
公开(公告)日：2019-01-24
申请号：US16034672
申请日：2018-07-13
申请人： Tomislav Suligoj , Tihomir Knezevic , Zeljko Osrecki
发明人： Tomislav Suligoj , Tihomir Knezevic , Zeljko Osrecki
IPC分类号： H01L27/146 , H01L31/107
摘要： A photodiode detector array comprises: a substrate comprising a front surface and a mounting surface; a first active region and a second active region, each of said first and second active regions being operatively configured to detect electromagnetic radiation in a wavelength range, and each of said first and second active regions being formed within said substrate and disposed proximate to said front surface; and a layer formed within said substrate and disposed proximal to said mounting surface, wherein said layer exhibits an electromagnetic wave absorption coefficient greater than or equal to 3×103 cm-1 in the wavelength range from 500 nm to 800 nm.

9. 发明申请

US20050040495A1 Horizontal current bipolar transistor and fabrication method 失效
标题翻译：水平电流双极晶体管及其制作方法
公开(公告)号：US20050040495A1
公开(公告)日：2005-02-24
申请号：US10677643
申请日：2003-10-01
申请人： Tomislav Suligoj , Petar Biljanovic , Kang Wang
发明人： Tomislav Suligoj , Petar Biljanovic , Kang Wang
IPC分类号： H01L21/331 , H01L29/10 , H01L29/735 , H01L29/00
CPC分类号： H01L29/6625 , H01L29/1008 , H01L29/735
摘要： A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.
摘要翻译：用于集成电路的双极晶体管结构，其中有源器件在n-hill的侧壁上被处理，使得表面覆盖区不依赖于有源器件区域（发射极区域）的期望区域。被称为水平电流双极晶体管（HCBT）的结构比常规器件消耗更小的芯片表面积，从而实现器件的更高的封装密度和/或集成电路管芯尺寸的降低。该器件采用单个多晶硅层制造，无需外延工艺，无需苛刻的沟槽隔离技术，并具有降低的热预算。与常规设备相比，制造需要更少的蚀刻工艺和热氧化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式