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    • 1. 发明申请
    • ELECTRONIC DEVICES
    • 电子设备
    • US20130299815A1
    • 2013-11-14
    • US13988399
    • 2011-11-25
    • Martin JacksonCatherine RamsdaleJerome Joimel
    • Martin JacksonCatherine RamsdaleJerome Joimel
    • H01L51/05
    • H01L51/0512H01L27/283H01L51/0541H01L51/0545
    • A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.
    • 一种包括晶体管阵列的器件,包括:位于衬底上的层叠层中的下层和上层的图案化导电层,所述图案化导电层限定晶体管阵列的栅极导体和源 - 漏电极; 其中所述层叠层还包括位于所述下层下面的电介质层,以及在所述介电层下方的另外的图案化导电层; 并且其中所述另外的图案化导电层都经由所述介电层在所述晶体管阵列中提供电功能,并且限定开口,所述介电层用于通过所述开口增加所述下层的器件基板和图案化导电层之间的粘合强度 。
    • 2. 发明授权
    • Electronic devices
    • 电子设备
    • US09130179B2
    • 2015-09-08
    • US13988399
    • 2011-11-25
    • Martin JacksonCatherine RamsdaleJerome Joimel
    • Martin JacksonCatherine RamsdaleJerome Joimel
    • H01L51/05H01L27/28
    • H01L51/0512H01L27/283H01L51/0541H01L51/0545
    • A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.
    • 一种包括晶体管阵列的器件,包括:位于衬底上的层叠层中的下层和上层的图案化导电层,所述图案化导电层限定晶体管阵列的栅极导体和源 - 漏电极; 其中所述层叠层还包括位于所述下层下面的电介质层,以及在所述介电层下方的另外的图案化导电层; 并且其中所述另外的图案化导电层都经由所述介电层在所述晶体管阵列中提供电功能,并且限定开口,所述介电层用于通过所述开口增加所述下层的器件基板和图案化导电层之间的粘合强度 。