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1. 发明授权

US11064435B1 Rapid sync up mechanism for traffic control between two systems 有权
公开(公告)号：US11064435B1
公开(公告)日：2021-07-13
申请号：US16264010
申请日：2019-01-31
申请人： Marvell International Ltd.
发明人： Yuanhua Deng , Zheng Cao , Xinyu Zang
IPC分类号： H04W48/02 , H04W52/02 , H04W88/12 , H04W56/00 , H04W40/24 , H04L1/16 , H04W84/12
摘要： Aspects of the disclosure provide methods and apparatuses for data communication. In some embodiments, an apparatus for data communication between a host and a plurality of station devices includes an interface circuit, a medium access controller (MAC) circuit, a control circuit, and a streaming circuit. The interface circuit is configured to receive a data packet from the host, and the data packet includes a bitmap addressing the data packet to one of the plurality of station devices. The medium access controller (MAC) circuit is configured to detect a sleep status of the one of the plurality of station devices. The control circuit is configured to adjust a bit mask based on the sleep status of the one of the plurality of station devices, so that the bit mask indicates the sleep status the one of the plurality of station devices. The streaming circuit is coupled between the interface circuit and the MAC circuit. The streaming circuit is configured to receive the data packet addressed to station devices, determine the sleep status of the one of the plurality of station devices based on the bit mask and the bitmap in the data packet, and transmit the data packet to the MAC circuit when the sleep status of the one of the plurality of station devices is in a wake state, otherwise, transmit the data packet to the control circuit when the sleep status of the one of the plurality of station devices is in a sleep state.

2. 发明授权

US11102680B1 Data transfer interface with reduced signaling 有权
公开(公告)号：US11102680B1
公开(公告)日：2021-08-24
申请号：US16427573
申请日：2019-05-31
申请人： Marvell International Ltd.
发明人： Frank Huang , Xinyu Zang , Benson Chau , Tao Song , Zheng Cao
IPC分类号： H04W28/14 , H04W80/02 , H04L12/861 , H04L1/18 , H04L12/801 , G06F13/14 , G06F3/06 , H04L12/835
摘要： A wireless data transceiver includes a media access controller (MAC) that receives an inbound packet from an air interface and to buffer that packet for transport to a host, and receives an outbound packet and transfers that packet to the air interface. A host interface receives the inbound packet from the MAC and transfers the inbound packet to the host, and receives the outbound packet from the host for transfer to the MAC. Transport controller circuitry (TCC), including processing circuitry configured to execute instructions, manages the transceiver. Hardware data transport circuitry (HDTC) for transporting packets in either direction between the MAC and the host interface includes a buffer memory having a plurality of slots. The TCC or HDTC issues a start or stop signal to the host interface causing the HDTC and the host interface to begin or end transfer of data between the buffer memory and the host interface.

3. 发明授权

US10820371B1 Hardware data transport in wireless data transceiver 有权
公开(公告)号：US10820371B1
公开(公告)日：2020-10-27
申请号：US16422298
申请日：2019-05-24
申请人： Marvell International Ltd.
发明人： Frank Huang , Tao Song , Xinyu Zang , Zheng Cao , James Kang-Wuu Jan
IPC分类号： H04W80/02 , H04W28/06 , H04W92/10 , H04W88/08 , H04L29/12
摘要： A wireless data transceiver includes a media access controller (MAC) configured to receive an inbound data packet from an air interface and to buffer the inbound packet for transport to a host, and to receive an outbound data packet from elsewhere in the transceiver and to transfer the outbound packet to the air interface. The transceiver further includes a host interface configured to receive the inbound packet transported from the MAC and to transfer the inbound packet to the host, and to receive the outbound packet from the host for transfer to the MAC. The transceiver also includes transport controller circuitry configured to execute instructions to generate and transfer management packets. In addition, the wireless data transceiver includes hardware data transport circuitry for transporting the inbound packet from the MAC to the host interface, and for transporting the outbound packet from the host interface to the MAC, without executing instructions.

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