专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10784167B2 Isolation components for transistors formed on fin features of semiconductor substrates 有权
公开(公告)号：US10784167B2
公开(公告)日：2020-09-22
申请号：US16230505
申请日：2018-12-21
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang , Chuan-Cheng Cheng
IPC分类号： H01L21/76 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L21/84 , H01L21/762 , H01L21/764 , H01L27/12 , H01L21/28
摘要： In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

2. 发明授权

US10600793B2 Fabricating memory devices with optimized gate oxide thickness 有权
公开(公告)号：US10600793B2
公开(公告)日：2020-03-24
申请号：US16397943
申请日：2019-04-29
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01L21/311 , H01L23/525 , H01L29/423 , H01L21/02 , H01L21/027
摘要： The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

3. 发明授权

US10522394B2 Method of creating aligned vias in ultra-high density integrated circuits 有权
公开(公告)号：US10522394B2
公开(公告)日：2019-12-31
申请号：US16106205
申请日：2018-08-21
申请人： Marvell World Trade LTD.
发明人： Runzi Chang , Min She
IPC分类号： H01L21/768 , H01L21/027 , H01L21/033 , H01L21/67 , H01L21/02 , H01L21/311 , H01L21/288
摘要： A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

4. 发明授权

US08873309B2 Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers 有权
标题翻译：用于修复电阻存储器并增加读出放大器的整体读出灵敏度的装置和方法
公开(公告)号：US08873309B2
公开(公告)日：2014-10-28
申请号：US14045230
申请日：2013-10-03
申请人： Marvell World Trade Ltd.
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： G11C16/04 , G11C29/02 , G11C7/06 , G11C13/00
CPC分类号： G11C7/065 , G11C7/06 , G11C7/067 , G11C7/1057 , G11C7/106 , G11C11/1653 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C29/026
摘要： A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.
摘要翻译：存储器包括模块和解复用器。该模块配置为监视读出放大器的输出。读出放大器的每个输出被配置为处于第一状态或第二状态。该模块被配置为确定读出放大器的两个或多个输出处于相同状态。相同的状态是第一个状态或第二个状态。该模块被配置为输出读出放大器的两个或多个输出的状态。解复用器被配置为将读出放大器的两个或更多个输出的状态提供给锁存器。

5. 发明申请

US20140170832A1 RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS 有权
标题翻译：电阻随机存取存储器及其控制方法，用于控制导电和电阻元件的相关分解特征的制造
公开(公告)号：US20140170832A1
公开(公告)日：2014-06-19
申请号：US14102922
申请日：2013-12-11
申请人： Marvell World Trade Ltd.
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L45/00 , H01L49/02
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/1675
摘要： A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.
摘要翻译：一种方法，包括：形成一层电阻层; 在形成电阻层堆叠之前或之后，形成导电层; 在电阻层或导电层的叠层上施加掩模层; 在掩模层上形成第一间隔物; 并且使用第一间隔件作为第一掩模蚀刻掉掩模层的第一部分以提供其余部分。该方法还包括：在电阻层或导电层和掩模层的其余部分的叠层上形成第二间隔物; 蚀刻掉掩模层的其余部分的第二部分以形成岛; 并且使用岛作为第二掩模，蚀刻电阻层的堆叠以形成存储器的电阻元件，并蚀刻导电层以形成存储器的导电元件。

6. 发明申请

US20140103452A1 ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：用于晶体管的分离元件在半导体衬底的特征上形成
公开(公告)号：US20140103452A1
公开(公告)日：2014-04-17
申请号：US14051299
申请日：2013-10-10
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang , Chuan-Cheng Cheng
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L21/823431 , H01L21/28035 , H01L21/76224 , H01L21/764 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795
摘要： In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm.
摘要翻译：在一个实施例中，一种装置包括基底，该基底包括具有平坦部分的表面和沿基本上垂直于该平面部分的方向延伸并且具有小于该基底的厚度的厚度的翅片特征。该装置还包括第一晶体管，其包括形成在鳍片特征上的第一栅极区域，由鳍状物体的主体形成的第一源极区域和由鳍状物体的主体形成的第一漏极区域。此外，该装置包括第二晶体管，其包括形成在鳍片特征上的第二栅极区域，由鳍片特征体形成的第二源极区域和由鳍片特征体形成的第二漏极区域。此外，该装置包括形成在第一晶体管和第二晶体管之间的隔离部件，其中隔离部件具有小于30nm的宽度。

7. 发明授权

US10784250B2 Sub-device field-effect transistor architecture for integrated circuits 有权
公开(公告)号：US10784250B2
公开(公告)日：2020-09-22
申请号：US16372905
申请日：2019-04-02
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/02 , H03K17/687
摘要： The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

8. 发明申请

US20190148236A1 Isolation Components for Transistors Formed on Fin Features of Semiconductor Substrates 审中-公开
公开(公告)号：US20190148236A1
公开(公告)日：2019-05-16
申请号：US16230505
申请日：2018-12-21
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang , Chuan-Cheng Cheng
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/12 , H01L21/764 , H01L29/66 , H01L21/84 , H01L27/088 , H01L21/762
CPC分类号： H01L21/823431 , H01L21/28035 , H01L21/76224 , H01L21/764 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795
摘要： In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

9. 发明申请

US20170351802A1 INTEGRATED CIRCUIT MANUFACTURING PROCESS FOR ALIGNING THRESHOLD VOLTAGES OF TRANSISTORS 审中-公开
公开(公告)号：US20170351802A1
公开(公告)日：2017-12-07
申请号：US15611628
申请日：2017-06-01
申请人： Marvell World Trade Ltd.
发明人： Runzi Chang , Winston Lee , Peter Lee
IPC分类号： G06F17/50 , G11C11/412
CPC分类号： G06F17/5077 , G06F2217/12 , G11C11/412 , H01L27/1104 , H01L27/1116
摘要： In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

10. 发明授权

US09490427B2 Resistive random access memory cell structure 有权
标题翻译：电阻式随机存取存储单元结构
公开(公告)号：US09490427B2
公开(公告)日：2016-11-08
申请号：US14955326
申请日：2015-12-01
申请人： Marvell World Trade LTD.
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Runzi Chang
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1273 , G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16 , Y10T29/49117
摘要： A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.
摘要翻译：一种包括存储单元的电阻元件和访问存储器单元的电阻元件的器件的系统。电阻元件包括（i）第一电极和（ii）第二电极。该装置包括（i）连接到第一触点的第一端子和（i）连接到第二触点的第二端子。器件的第一接触和第二接触中的一个或多个分别经由第三接触连接到电阻元件的第一电极和第二电极中的一个或多个。第三接触的尺寸从器件的第一接触和第二接触中的一个或多个减小到存储器单元的电阻元件的第一电极和第二电极中的一个或多个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式