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1. 发明授权

US08498500B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US08498500B2
公开(公告)日：2013-07-30
申请号：US13496274
申请日：2010-04-28
申请人： Masashi Hoshino , Shuichi Takada
发明人： Masashi Hoshino , Shuichi Takada
IPC分类号： G06K9/36
CPC分类号： G09G5/397 , G06T3/40 , G09G5/14 , H04N1/3935
摘要： An image processing apparatus includes a blending layout information generating unit that generates blending layout information indicative of overlay information in a blended image of plural source images, a source necessity information generating unit that generates source necessity information indicative of unnecessary areas on the source image overwritten by the blending process, a source necessity information storing memory, and a source read masking unit that conducts a read masking control. A process of generating the blending layout information and the source necessity information, and a process of conducting the read masking control are executed in different frame processing periods, separately, to reduce a throughput necessary for generation of the source necessity information.
摘要翻译：一种图像处理装置，包括：混合布局信息生成单元，生成表示多个源图像的混合图像中的重叠信息的混合布局信息;源必需信息生成单元，生成表示源图像上的不必要区域的源必需信息，混合处理，源必要性信息存储存储器，以及进行读取掩蔽控制的源读取屏蔽单元。生成混合布局信息和源必要性信息的处理以及执行读取屏蔽控制的处理分别在不同的帧处理周期中执行，以减少产生源必要性信息所需的吞吐量。

2. 发明申请

US20120163732A1 IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US20120163732A1
公开(公告)日：2012-06-28
申请号：US13496274
申请日：2010-04-28
申请人： Masashi Hoshino , Shuichi Takada
发明人： Masashi Hoshino , Shuichi Takada
IPC分类号： G06K9/36
CPC分类号： G09G5/397 , G06T3/40 , G09G5/14 , H04N1/3935
摘要： An image processing apparatus includes a blending layout information generating unit that generates blending layout information indicative of overlay information in a blended image of plural source images, a source necessity information generating unit that generates source necessity information indicative of unnecessary areas on the source image overwritten by the blending process, a source necessity information storing memory, and a source read masking unit that conducts a read masking control. A process of generating the blending layout information and the source necessity information, and a process of conducting the read masking control are executed in different frame processing periods, separately, to reduce a throughput necessary for generation of the source necessity information.
摘要翻译：一种图像处理装置，包括：混合布局信息生成单元，生成表示多个源图像的混合图像中的重叠信息的混合布局信息;源必需信息生成单元，生成表示源图像上的不必要区域的源必需信息，混合处理，源必要性信息存储存储器，以及进行读取掩蔽控制的源读取屏蔽单元。生成混合布局信息和源必要性信息的处理以及执行读取屏蔽控制的处理分别在不同的帧处理周期中执行，以减少产生源必要性信息所需的吞吐量。

3. 发明授权

US08374305B2 Clock recovery circuit and data recovery circuit 失效
标题翻译：时钟恢复电路和数据恢复电路
公开(公告)号：US08374305B2
公开(公告)日：2013-02-12
申请号：US12717449
申请日：2010-03-04
申请人： Shuichi Takada
发明人： Shuichi Takada
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091
摘要： A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a lower frequency, to output a parallel phase information signal. A digital filtering circuit calculates phase deviation and phase advance-delay signals based on the parallel phase information signal in synchronization with the second clock signal. By these signals, a phase control amount processing circuit generates a phase control signal. The phase control signal is in synchronization with third clock signals having a higher frequency. A phase interpolation circuit adjusts the phases of the third clock signals based on the phase control signal to output the first clock signals.
摘要翻译：串行输入信号与多个第一时钟信号同步地采样，以获得多个采样数据。相位比较电路根据采样数据输出串行相位信息信号。串行并行转换电路与具有较低频率的第二时钟信号同步地对串行相位信息信号进行串行 - 并行转换，以输出并行相位信息信号。数字滤波电路与第二时钟信号同步地基于并行相位信息信号计算相位偏差和相位超前延迟信号。通过这些信号，相位控制量处理电路产生相位控制信号。相位控制信号与具有较高频率的第三时钟信号同步。相位插值电路基于相位控制信号来调整第三时钟信号的相位，以输出第一时钟信号。

4. 发明申请

US20110064176A1 CLOCK RECOVERY CIRCUIT AND DATA RECOVERY CIRCUIT 失效
标题翻译：时钟恢复电路和数据恢复电路
公开(公告)号：US20110064176A1
公开(公告)日：2011-03-17
申请号：US12717449
申请日：2010-03-04
申请人： Shuichi Takada
发明人： Shuichi Takada
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091
摘要： A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a lower frequency, to output a parallel phase information signal. A digital filtering circuit calculates phase deviation and phase advance-delay signals based on the parallel phase information signal in synchronization with the second clock signal. By these signals, a phase control amount processing circuit generates a phase control signal. The phase control signal is in synchronization with third clock signals having a higher frequency. A phase interpolation circuit adjusts the phases of the third clock signals based on the phase control signal to output the first clock signals.
摘要翻译：串行输入信号与多个第一时钟信号同步地采样，以获得多个采样数据。相位比较电路根据采样数据输出串行相位信息信号。串行并行转换电路与具有较低频率的第二时钟信号同步地对串行相位信息信号进行串行 - 并行转换，以输出并行相位信息信号。数字滤波电路与第二时钟信号同步地基于并行相位信息信号来计算相位偏差和相位超前延迟信号。通过这些信号，相位控制量处理电路产生相位控制信号。相位控制信号与具有较高频率的第三时钟信号同步。相位插值电路基于相位控制信号来调整第三时钟信号的相位，以输出第一时钟信号。

5. 发明申请

US20100327973A1 AMPLIFIER CIRCUIT COMPRISING CHARGE PUMP AND LOW-PASS FILTER 审中-公开
标题翻译：包括充电泵和低通滤波器的放大器电路
公开(公告)号：US20100327973A1
公开(公告)日：2010-12-30
申请号：US12819509
申请日：2010-06-21
申请人： Shuichi Takada
发明人： Shuichi Takada
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： According to one embodiment, an amplifier circuit includes a clock generation circuit, a switching amplifier circuit, and a smoothing circuit. The clock generation circuit generates a pseudo random period pattern signal whose period varies. The switching amplifier circuit samples an input signal based on the pseudo random period pattern signal used as a sampling clock. The smoothing circuit smoothes an output signal of the switching amplifier circuit.
摘要翻译：根据一个实施例，放大器电路包括时钟产生电路，开关放大器电路和平滑电路。时钟产生电路产生周期变化的伪随机周期模式信号。开关放大器电路基于用作采样时钟的伪随机周期模式信号对输入信号进行采样。平滑电路平滑开关放大器电路的输出信号。

6. 发明申请

US20100245245A1 SPATIAL INPUT OPERATION DISPLAY APPARATUS 审中-公开
标题翻译：空间输入操作显示装置
公开(公告)号：US20100245245A1
公开(公告)日：2010-09-30
申请号：US12745765
申请日：2008-12-10
申请人： Tomiyuki Yamada , Shuichi Takada , Shunsaku Imaki
发明人： Tomiyuki Yamada , Shuichi Takada , Shunsaku Imaki
IPC分类号： G06F3/033
CPC分类号： G06F3/011 , G06F3/033 , G06K9/00375
摘要： A spatial input operation display apparatus providing a user interface allowing input operations inside a space without requiring hands or fingers to be stopped in space, and not requiring a physical shape or space. The spatial input operation display apparatus is provided with a shape identifying portion (102) for recognizing shapes by comparing images obtained by a camera (101) with data stored in a shape data storing portion (103), an operation identifying portion (105) for identifying and anticipating motion patterns by comparing differential vector data of data identified by the shape identifying portion (102) with differential vector data stored in a motion data storing portion (106), a controller (107) for outputting image data based on motion pattern data of the operation identifying portion (105) and position data of an identified data storing portion (104), an image generating portion (108) for generating images by performing processes including rotation and expansion based on selected image data, and a display portion (109) for displaying the generated images to a space.
摘要翻译：一种空间输入操作显示装置，其提供允许在空间内进行输入操作的用户界面，而不需要在空间中停止手或手指，并且不需要物理形状或空间。空间输入操作显示装置设置有形状识别部分（102），用于通过将由相机（101）获得的图像与存储在形状数据存储部分（103）中的数据进行比较来识别形状;操作识别部分（105），用于通过将由形状识别部分（102）识别的数据的差分矢量数据与存储在运动数据存储部分（106）中的差分矢量数据相比较来识别和预测运动模式，用于基于运动模式数据输出图像数据的控制器操作识别部分（105）和识别数据存储部分（104）的位置数据，以及用于通过基于所选择的图像数据执行包括旋转和扩展的处理来产生图像的图像生成部分（108），以及显示部分），用于将生成的图像显示到空间。

7. 发明授权

US07990295B2 Data transfer apparatus 失效
标题翻译：数据传输装置
公开(公告)号：US07990295B2
公开(公告)日：2011-08-02
申请号：US12717593
申请日：2010-03-04
申请人： Shuichi Takada
发明人： Shuichi Takada
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit.
摘要翻译：数据传送装置包括：时钟生成单元，生成时钟信号;控制单元，输出并行数据和复位信号;多个发送单元。多个传输单元中的每一个使用位时钟的连续上升沿多次对复位信号进行采样，从而减少了传输单元之间的复位信号的相移，并且分频时钟的相位在每个传输单元。

8. 发明授权

US07853836B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07853836B2
公开(公告)日：2010-12-14
申请号：US12047753
申请日：2008-03-13
申请人： Shuichi Takada
发明人： Shuichi Takada
IPC分类号： G11B20/20 , G01R31/28
CPC分类号： G01R31/31709 , G01R31/31727 , H03L7/07 , H03L7/0812 , H03L7/183 , H04L1/244
摘要： A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.
摘要翻译：半导体集成电路包括产生第一时钟的时钟发生器，调制第一时钟的相位的测试数据发生器，并且通过使用调制时钟生成添加了抖动的测试数据;对测试数据进行采样的数据提取器并提取恢复数据，以及检测器，其检测恢复数据的错误。

9. 发明授权

US07473987B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07473987B2
公开(公告)日：2009-01-06
申请号：US11398352
申请日：2006-04-04
申请人： Shingo Takagi , Shuichi Takada
发明人： Shingo Takagi , Shuichi Takada
IPC分类号： H01L23/48
CPC分类号： G11C8/08 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, there is provided a semiconductor device comprising: a current driver which is connected to a power supply terminal, and supplies a predetermined current; a first wiring layer which is connected to an output terminal of said current driver; and a second wiring layer which is placed to oppose said first wiring layer via an insulating layer, and has a predetermined resistance value.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电流驱动器，其连接到电源端子，并提供预定电流; 连接到所述电流驱动器的输出端的第一布线层; 以及第二布线层，其被配置成经由绝缘层与所述第一布线层相对，并且具有预定的电阻值。

10. 发明申请

US20060262596A1 Semiconductor device 失效
公开(公告)号：US20060262596A1
公开(公告)日：2006-11-23
申请号：US11398352
申请日：2006-04-04
申请人： Shingo Takagi , Shuichi Takada
发明人： Shingo Takagi , Shuichi Takada
IPC分类号： G11C11/14
CPC分类号： G11C8/08 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, there is provided a semiconductor device comprising: a current driver which is connected to a power supply terminal, and supplies a predetermined current; a first wiring layer which is connected to an output terminal of said current driver; and a second wiring layer which is placed to oppose said first wiring layer via an insulating layer, and has a predetermined resistance value.

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