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1. 发明授权

US08635417B2 Memory system including variable write command scheduling 有权
标题翻译：内存系统包括可变写入命令调度
公开(公告)号：US08635417B2
公开(公告)日：2014-01-21
申请号：US13468850
申请日：2012-05-10
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括多个存储器写入命令类型。每个存储器写入命令类型对应于用于传送对应的数据有效载荷的不同的相应调度。

2. 发明申请

US20110191647A1 COMMUNICATION INTERFACE AND PROTOCOL 有权
标题翻译：通信接口和协议
公开(公告)号：US20110191647A1
公开(公告)日：2011-08-04
申请号：US12697763
申请日：2010-02-01
申请人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
发明人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
IPC分类号： H04L1/18 , G06F11/07 , G08C25/02
CPC分类号： H04L1/1607 , H04L2001/0096 , H04L2001/125
摘要： An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.
摘要翻译：一种装置包括接收机，错误检测单元和确认单元。接收机可以经由第一通信路径从第二装置的发射机单元接收数据帧。错误检测单元可以检测通过第一通信路径接收的数据的帧中的数据错误。确认单元可以保持指示由设备接收的帧是否是无错误的确认指示符。响应于错误检测单元检测到错误，确认单元可以通过冻结确认指示符的值来指示存在错误状况，或者可选地，确认单元可以将确认指示符的当前值设置为预定的错误值。此外，当设备正在接收帧时，该设备可以经由第二通信路径将确认指示符的值连续传送到第二设备。

3. 发明申请

US20110191619A1 Reducing Latency in Serializer-Deserializer Links 有权
标题翻译：在Serializer-Deserializer链接中减少延迟
公开(公告)号：US20110191619A1
公开(公告)日：2011-08-04
申请号：US12697223
申请日：2010-01-30
申请人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
发明人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
IPC分类号： G06F13/42 , G06F1/04
CPC分类号： G11C7/1012 , G11C2207/107 , H03M9/00 , H04J3/0685 , H04L25/14
摘要： A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
摘要翻译：一种用于通过串行器 - 解串器（SerDes）链路提高数据传输效率的系统，并且用于减少由SerDes链路上的数据到达时间与设备运行的系统时钟之间的差异导致的数据延迟。

4. 发明授权

US08473695B2 Memory system including variable write command scheduling 有权
标题翻译：内存系统包括可变写入命令调度
公开(公告)号：US08473695B2
公开(公告)日：2013-06-25
申请号：US13077261
申请日：2011-03-31
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括多个存储器写入命令类型。每个存储器写入命令类型对应于用于传送对应的数据有效载荷的不同的相应调度。

5. 发明申请

US20120254558A1 MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING 有权
标题翻译：包括可变写入命令调度的存储系统
公开(公告)号：US20120254558A1
公开(公告)日：2012-10-04
申请号：US13468850
申请日：2012-05-10
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括多个存储器写入命令类型。每个存储器写入命令类型对应于用于传送对应的数据有效载荷的不同的相应调度。

6. 发明授权

US08832336B2 Reducing latency in serializer-deserializer links 有权
标题翻译：在串行器解串器链接中减少延迟
公开(公告)号：US08832336B2
公开(公告)日：2014-09-09
申请号：US12697223
申请日：2010-01-30
申请人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
发明人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G11C7/1012 , G11C2207/107 , H03M9/00 , H04J3/0685 , H04L25/14
摘要： A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
摘要翻译：一种用于通过串行器 - 解串器（SerDes）链路提高数据传输效率的系统，并且用于减少由SerDes链路上的数据到达时间与设备运行的系统时钟之间的差异导致的数据延迟。

7. 发明授权

US08527676B2 Reducing latency in serializer-deserializer links 有权
标题翻译：在串行器解串器链接中减少延迟
公开(公告)号：US08527676B2
公开(公告)日：2013-09-03
申请号：US13467955
申请日：2012-05-09
申请人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
发明人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
IPC分类号： G06F13/38 , G06F15/16 , G06F13/00
CPC分类号： G11C7/1012 , G11C2207/107 , H03M9/00 , H04J3/0685 , H04L25/14
摘要： A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
摘要翻译：一种用于通过串行器 - 解串器（SerDes）链路提高数据传输效率的系统，并且用于减少由SerDes链路上的数据到达时间与设备运行的系统时钟之间的差异导致的数据延迟。

8. 发明授权

US08370725B2 Communication interface and protocol 有权
标题翻译：通信接口和协议
公开(公告)号：US08370725B2
公开(公告)日：2013-02-05
申请号：US12697763
申请日：2010-02-01
申请人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
发明人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
IPC分类号： G11C13/00
CPC分类号： H04L1/1607 , H04L2001/0096 , H04L2001/125
摘要： An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.
摘要翻译：一种装置包括接收机，错误检测单元和确认单元。接收机可以经由第一通信路径从第二装置的发射机单元接收数据帧。错误检测单元可以检测通过第一通信路径接收的数据的帧中的数据错误。确认单元可以保持指示由设备接收的帧是否是无错误的确认指示符。响应于错误检测单元检测到错误，确认单元可以通过冻结确认指示符的值来指示存在错误条件，或者可选地，确认单元可以将确认指示符的当前值设置为预定的错误值。此外，当设备正在接收帧时，该设备可以经由第二通信路径将确认指示符的值连续传送到第二设备。

9. 发明申请

US20120254562A1 MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING 有权
公开(公告)号：US20120254562A1
公开(公告)日：2012-10-04
申请号：US13077261
申请日：2011-03-31
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.

10. 发明申请

US20120221882A1 Reducing Latency In Serializer-Deserializer Links 有权
标题翻译：在Serializer-Deserializer链接中减少延迟
公开(公告)号：US20120221882A1
公开(公告)日：2012-08-30
申请号：US13467955
申请日：2012-05-09
申请人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
发明人： Michael J. Morrison , Jay B. Patel , Philip A. Ferolito , Michael J. Miller
IPC分类号： G06F1/04
CPC分类号： G11C7/1012 , G11C2207/107 , H03M9/00 , H04J3/0685 , H04L25/14
摘要： A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
摘要翻译：一种用于通过串行器 - 解串器（SerDes）链路提高数据传输效率的系统，并且用于减少由SerDes链路上的数据到达时间与设备运行的系统时钟之间的差异导致的数据延迟。

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