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1. 发明申请

US20060153195A1 Sequencer and method for sequencing 有权
标题翻译：测序仪和测序方法
公开(公告)号：US20060153195A1
公开(公告)日：2006-07-13
申请号：US11022252
申请日：2004-12-23
申请人： Michael Rytting , Glenn Wood
发明人： Michael Rytting , Glenn Wood
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G01R31/3177
摘要： A method and apparatus for sequencing determines possible next states for respective possible previous states based upon resources, selects one of the possible next states as an actual next state based upon an actual previous state, and communicates the actual next state as the actual previous state.
摘要翻译：用于排序的方法和装置基于资源确定各个可能的先前状态的可能的下一状态，基于实际的先前状态选择可能的下一状态之一作为实际的下一状态，并将实际的下一状态作为实际的先前状态进行通信。

2. 发明申请

US20060236148A1 One hot counter proxy 审中-公开
标题翻译：一个热计数器代理
公开(公告)号：US20060236148A1
公开(公告)日：2006-10-19
申请号：US11040556
申请日：2005-01-21
申请人： Glenn Wood , Michael Rytting
发明人： Glenn Wood , Michael Rytting
IPC分类号： G06F1/14
CPC分类号： G01R31/3177
摘要： A method and apparatus for sequencing includes sequencing elements in rippled combination, each sequencing element processing a subset of de-multiplexed incoming data over a single resource cycle. Each sequencing element processes a one hot counter proxy that represents a sequencer counter.
摘要翻译：用于测序的方法和装置包括波纹组合中的测序元件，每个测序元件在单个资源周期处理解复用的输入数据的子集。每个排序元素处理一个代表定序器计数器的热计数器代理。

3. 发明授权

US07684447B2 Sequencer and method for sequencing 有权
标题翻译：测序仪和测序方法
公开(公告)号：US07684447B2
公开(公告)日：2010-03-23
申请号：US11022252
申请日：2004-12-23
申请人： Michael Rytting , Glenn Wood
发明人： Michael Rytting , Glenn Wood
IPC分类号： H04J3/04 , G06F11/00
CPC分类号： G01R31/3177
摘要： A method and apparatus for sequencing determines possible next states for respective possible previous states based upon resources, selects one of the possible next states as an actual next state based upon an actual previous state, and communicates the actual next state as the actual previous state.
摘要翻译：用于排序的方法和装置基于资源确定各个可能的先前状态的可能的下一状态，基于实际的先前状态选择可能的下一状态之一作为实际的下一状态，并将实际的下一状态作为实际的先前状态进行通信。

4. 发明申请

US20060153248A1 Counter proxy 审中-公开
标题翻译：柜台代理
公开(公告)号：US20060153248A1
公开(公告)日：2006-07-13
申请号：US11022224
申请日：2004-12-23
申请人： Michael Rytting , Glenn Wood
发明人： Michael Rytting , Glenn Wood
IPC分类号： H04J3/04
CPC分类号： G01R31/3177
摘要： A method and apparatus for sequencing generates a counter proxy from a counter, processes the counter proxy through multiple sequencing elements, and restores coherency of the counter from said counter proxy after processing the counter proxy and before another processing step.
摘要翻译：一种用于排序的方法和装置从计数器生成计数器代理，通过多个排序元件处理计数器代理，并且在处理计数器代理之后并且在另一个处理步骤之前恢复来自所述计数器代理的计数器的一致性。

5. 发明授权

US06774700B1 Current-mode logic differential signal generation circuit employing squelch 失效
标题翻译：采用静噪的电流模式逻辑差分信号发生电路
公开(公告)号：US06774700B1
公开(公告)日：2004-08-10
申请号：US10651675
申请日：2003-08-29
申请人： Glenn Wood
发明人： Glenn Wood
IPC分类号： H03K1762
CPC分类号： H04L25/0282 , H04L25/0276 , H04L25/0278
摘要： An electrical circuit generates both a differential data signal and a “squelch,” or “out-of-band,” state over a differential signal pair by employing common-mode logic (CML) technology. In one embodiment of the invention, a CML buffer having true and complementary (inverted) data outputs drive the differential data signal onto the positive (‘p’) and negative (‘n’) signal lines of the differential pair. To implement the squelch state, the true and complementary outputs of a two-input CML multiplexer are coupled with the corresponding outputs of the buffer. The data inputs of the multiplexer are driven by the data input signal driving the buffer, as well as the logical inversion of the data input signal. A squelch state signal then drives an input selector of the multiplexer to impress the squelch state over the differential signal pair when active.
摘要翻译：电路通过采用共模逻辑（CML）技术在差分信号对上产生差分数据信号和“静噪”或“带外”状态。在本发明的一个实施例中，具有真实和互补（反相）数据输出的CML缓冲器将差分数据信号驱动到差分对的正（“p”）和负（“n”）信号线上。为了实现静噪状态，双输入CML多路复用器的真实和互补输出与缓冲器的相应输出耦合。多路复用器的数据输入由驱动缓冲器的数据输入信号以及数据输入信号的逻辑反相驱动。然后，静噪状态信号驱动复用器的输入选择器，以在激活时对差分信号对施加静噪状态。

6. 发明申请

US20050243905A1 Bounding box signal detector 失效
标题翻译：边界箱信号检测器
公开(公告)号：US20050243905A1
公开(公告)日：2005-11-03
申请号：US10834678
申请日：2004-04-28
申请人： Glenn Wood , David Eskeldson
发明人： Glenn Wood , David Eskeldson
IPC分类号： G01R13/00 , G01R13/34 , G01R31/319 , G01R31/3193 , H03K5/08 , H04B1/69
CPC分类号： H03K5/08 , G01R31/31922 , G01R31/31937
摘要： A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose vertices are identified by threshold crossings offset for the voltage of interest and clocked by time delays offset from a clock time of interest. A first set of latches clocked by the time delays accumulates the state of signal behavior relative to the threshold voltages as it occurs, and their contents are subsequently transferred to a second set of latches at the start of a new clock cycle, allowing a new accumulation to begin and also allowing a detection logic circuit to operate on a unified and completed collection of indicators of what the just concluded description amounts to. The detection logic circuit responds to the combinations of latched indications to produce a signal corresponding to that description. The closed figure need not be a rectangle, and it may also serve as an indication that a signal went into a region that it should not have, e.g., an eye violation detector.
摘要翻译：通过在（时间，电压）平面中定义作为关闭的直边图形的区域来产生在感兴趣的时间和电压附近的信号行为的描述，其顶点通过针对感兴趣的电压的阈值交叉偏移来识别，时钟延迟偏离感兴趣的时钟时间。由时间延迟计时的第一组锁存器在其出现时累积相对于阈值电压的信号行为状态，并且其内容随后在新时钟周期开始时传送到第二组锁存器，从而允许新的累加开始并允许检测逻辑电路对刚刚结束的描述所达到的统一和完整的指标集合进行操作。检测逻辑电路响应锁存指示的组合以产生对应于该描述的信号。闭合图不必是矩形，并且它也可以用作信号进入不应该具有的区域的指示，例如眼睛违规检测器。

7. 发明申请

US20050047499A1 System and method for measuring the response time of a differential signal pair squelch detection circuit 审中-公开
标题翻译：用于测量差分信号对静噪检测电路的响应时间的系统和方法
公开(公告)号：US20050047499A1
公开(公告)日：2005-03-03
申请号：US10651741
申请日：2003-08-29
申请人： Glenn Wood
发明人： Glenn Wood
IPC分类号： G01R31/317 , G01R31/3193 , H03G3/34 , H03G7/00 , H04B17/00
CPC分类号： G01R31/31725 , G01R31/31937 , H03G3/34 , H03G7/007
摘要： A system and method for measuring the response time of a differential signal pair squelch detection circuit is provided. First, both the positive and negative signal lines of the differential signal pair are driven with square waves of different frequencies, typically by way of a signal generator. Thereafter, either the phase or the frequency of the two square waves is gradually altered until the duty cycle of a squelch detect signal of the squelch detection circuit falls below fifty percent. The resulting period of the square waves, or the relative phase between the two, is then utilized to calculate the response time of the squelch detection circuit.
摘要翻译：提供了一种用于测量差分信号对静噪检测电路的响应时间的系统和方法。首先，差分信号对的正和负信号线都以不同频率的方波来驱动，通常是通过信号发生器。此后，两个方波的相位或频率都逐渐改变，直到静噪检测电路的静噪检测信号的占空比下降到50％以下。然后利用所产生的方波周期或两者之间的相对相位来计算静噪检测电路的响应时间。

8. 发明授权

US07372931B2 Unit interval discovery for a bus receiver 失效
标题翻译：总线接收器的单位间隔发现
公开(公告)号：US07372931B2
公开(公告)日：2008-05-13
申请号：US10815139
申请日：2004-03-31
申请人： Glenn Wood
发明人： Glenn Wood
IPC分类号： H03M71/00
CPC分类号： H03M7/04
摘要： A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective cells of a sticky ONES (SONE) register previously initialized to all ZEROS. SZERO measures the unit interval of a ONE.
摘要翻译：总线数据信号被应用于抽头数据延迟线。存在于延迟线的抽头处的各种日益延迟的数据值被计时到先前初始化为所有ONES的粘性ZERO寄存器（SZERO）的相应单元中，并且进入先前初始化为所有ZEROS的粘性ONES（SONE）寄存器的相应单元格中。 SZERO测量ONE的单位间隔。

9. 发明授权

US07183781B2 Incorporation of isolation resistor(s) into probes using probe tip spring pins 失效
标题翻译：使用探头尖端弹簧针将隔离电阻并入探头
公开(公告)号：US07183781B2
公开(公告)日：2007-02-27
申请号：US10918285
申请日：2004-08-13
申请人： Brock J. LaMeres , Brent Holcombe , Glenn Wood
发明人： Brock J. LaMeres , Brent Holcombe , Glenn Wood
IPC分类号： G01R31/02
CPC分类号： G01R1/07328 , G01R1/06716 , G01R1/06766 , H05K1/115 , H05K1/167 , H05K2201/09518 , H05K2201/09536 , H05K2201/09627
摘要： An isolation resistor is incorporated into the plunger of a probe tip spring pin by, for example, doping a ceramic that is used to form the plunger, or forming the plunger of first and second electrically coupled materials, at least a first of which has a resistivity sufficient to serve as an isolation resistor. Alternately, an isolation resistor is embedded in a printed circuit board trace that is used to couple either an upper or lower blind plated hole to a via. A probe tip spring pin is then inserted into the upper blind plated hole.
摘要翻译：通过例如掺杂用于形成柱塞的陶瓷或形成第一和第二电耦合材料的柱塞，将隔离电阻器并入到探针针尖弹簧销的柱塞中，其至少第一个具有电阻率足以用作隔离电阻。或者，隔离电阻器嵌入印刷电路板迹线中，该迹线用于将上部或下部盲孔电镀孔连接到通孔。然后将探头尖弹簧销插入上盲孔镀孔。

10. 发明授权

US07120408B2 Differential signal squelch detection circuit and method 失效
标题翻译：差分信号静噪检测电路及方法
公开(公告)号：US07120408B2
公开(公告)日：2006-10-10
申请号：US10631690
申请日：2003-07-31
申请人： Glenn Wood
发明人： Glenn Wood
IPC分类号： H04B1/10
CPC分类号： H04L25/085 , H04L25/0276 , H04L25/0292
摘要： An electrical circuit detects a “squelch,” or “out-of-band,” state of a differential signal pair having a positive (“p”) signal line and a negative (“n”) signal line. In one embodiment of the invention, a first and a second comparator each have positive inputs driven by the positive and negative signal lines, respectively. The negative inputs of the comparators are driven by the outputs of separate digital-to-analog converters (DACs) which are set to a lower squelch threshold voltage. The outputs of the comparators then drive the inputs of a logical AND gate, the output of which indicates the current squelch state of the differential signal pair.
摘要翻译：电路检测到具有正（“p”）信号线和负（“n”）信号线的差分信号对的“静噪”或“带外”状态。在本发明的一个实施例中，第一和第二比较器分别具有由正和负信号线驱动的正输入。比较器的负输入由分立的数模转换器（DAC）的输出驱动，分压数模转换器（DAC）被设置为较低的静噪阈值电压。然后，比较器的输出驱动逻辑与门的输入，其输出指示差分信号对的当前静噪状态。

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