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1. 发明申请

US20100044868A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100044868A1
公开(公告)日：2010-02-25
申请号：US12477601
申请日：2009-06-03
申请人： Hiroshi NASU , Minoru Fujisaku , Michinari Tetani , Hyoe Ueda , Hisashi Takahashi
发明人： Hiroshi NASU , Minoru Fujisaku , Michinari Tetani , Hyoe Ueda , Hisashi Takahashi
IPC分类号： H01L23/522
CPC分类号： H01L23/525 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03614 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05015 , H01L2224/05022 , H01L2224/05099 , H01L2224/05552 , H01L2224/05562 , H01L2224/05571 , H01L2224/05599 , H01L2224/131 , H01L2224/81097 , H01L2224/81815 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/10329 , H01L2924/12036 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/3025 , H01L2924/381 , H01L2924/01014 , H01L2924/00
摘要： A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through the conductor. The second interconnection is positioned below the first interconnections and the electrode. The semiconductor device has a region where the shortest distance between an edge surface of the electrode and an edge surface of one of the first interconnections positioned most adjacent to the electrode is less than 0.11 times the total thickness of the conductor and the electrode. The second interconnection is positioned at a position different from that of the region in a thickness direction of the semiconductor device.
摘要翻译：半导体器件包括外部端子，多个第一互连，电极，导体和第二互连。第一互连位于外部端子的下方。电极位于与第一互连相同的水平面上，并通过导体与外部端子电连接。第二互连位于第一互连和电极之下。半导体器件具有电极的边缘表面和位于最靠近电极的第一互连中的一个的边缘表面之间的最短距离小于导体和电极的总厚度的0.11倍的区域。第二互连位于与半导体器件的厚度方向上的区域不同的位置。

2. 发明授权

US08084859B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08084859B2
公开(公告)日：2011-12-27
申请号：US12207790
申请日：2008-09-10
申请人： Michinari Tetani , Minoru Fujisaku
发明人： Michinari Tetani , Minoru Fujisaku
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L23/3114 , H01L23/522 , H01L23/5227 , H01L23/525 , H01L23/562 , H01L23/645 , H01L24/12 , H01L2224/0401 , H01L2224/05555 , H01L2224/11 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/12036 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H01L2924/00
摘要： In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.
摘要翻译：在晶片级CSP封装中，相对于设置在封装外周部分的外部输出端子附近的信号布线禁止区域16中的信号布线9b，由于在信号布线9处产生的应力可以通过布置信号布线9b周围的虚拟布线9a或通过扩大信号布线本身的宽度，可以容易地抑制表面保护膜中的裂纹的发生。

3. 发明申请

US20090096094A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090096094A1
公开(公告)日：2009-04-16
申请号：US12207790
申请日：2008-09-10
申请人： Michinari Tetani , Minoru Fujisaku
发明人： Michinari Tetani , Minoru Fujisaku
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/3114 , H01L23/522 , H01L23/5227 , H01L23/525 , H01L23/562 , H01L23/645 , H01L24/12 , H01L2224/0401 , H01L2224/05555 , H01L2224/11 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/12036 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H01L2924/00
摘要： In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.
摘要翻译：在晶片级CSP封装中，相对于设置在封装外周部分的外部输出端子附近的信号布线禁止区域16中的信号布线9b，由于在信号布线9处产生的应力可以通过布置信号布线9b周围的虚拟布线9a或通过扩大信号布线本身的宽度，可以容易地抑制表面保护膜中的裂纹的发生。

4. 发明申请

US20060268530A1 Wiring board, semiconductor device and display module 失效
标题翻译：接线板，半导体器件和显示模块
公开(公告)号：US20060268530A1
公开(公告)日：2006-11-30
申请号：US11441678
申请日：2006-05-26
申请人： Kouichi Nagao , Yoshifumi Nakamura , Hiroyuki Imamura , Michinari Tetani
发明人： Kouichi Nagao , Yoshifumi Nakamura , Hiroyuki Imamura , Michinari Tetani
IPC分类号： H05K1/03 , H05K1/09
CPC分类号： H05K1/028 , H01L2224/73204 , H05K1/111 , H05K1/189 , H05K3/025 , H05K3/243 , H05K3/28 , H05K3/382 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , Y02P70/611
摘要： A wiring board includes: a flexible insulating base 1; a plurality of conductive wirings 2 arranged on the flexible insulating base 1; protruding electrodes 3 provided respectively at an end portion of the same side of each of the conductive wirings; external terminals 4, 5 formed respectively at the other end portions of each of the conductive wirings; metal plating layers applied on the conductive wirings, the protruding electrodes and the external terminals; and solder resist layers 7 formed respectively by coating the conductive wirings in regions between the end portions at which the protruding electrodes are provided and the external terminals. In the regions where the solder resist layers are formed, no metal plating layers are formed on the conductive wirings, and the surfaces of the conductive wirings to be contacted with the flexible insulating base are rougher than the surfaces not to be contacted with the flexible insulating base. Even when a film base is thin, bending stress applied to the conductive wirings is relieved sufficiently, and thus breaks in the wirings are suppressed.
摘要翻译：布线板包括：柔性绝缘基座1; 布置在柔性绝缘基座1上的多个导电布线2; 突出电极3分别设置在每个导电布线的同一侧的端部处; 外部端子4,5分别形成在每个导电布线的另一端部; 施加在导电布线，突出电极和外部端子上的金属镀层; 以及分别通过在设置有突出电极的端部与外部端子之间的区域中涂覆导电布线而形成的阻焊层7。在形成阻焊层的区域中，在导电布线上不形成金属镀层，与挠性绝缘基体接触的导电配线的表面比不与柔性绝缘体接触的表面更粗糙基础。即使当薄膜基底较薄时，施加到导电布线的弯曲应力被充分地减轻，因此抑制布线中断。

5. 发明授权

US07250575B2 Wiring board, semiconductor device and display module 失效
标题翻译：接线板，半导体器件和显示模块
公开(公告)号：US07250575B2
公开(公告)日：2007-07-31
申请号：US11441678
申请日：2006-05-26
申请人： Kouichi Nagao , Yoshifumi Nakamura , Hiroyuki Imamura , Michinari Tetani
发明人： Kouichi Nagao , Yoshifumi Nakamura , Hiroyuki Imamura , Michinari Tetani
IPC分类号： H05K3/46
CPC分类号： H05K1/028 , H01L2224/73204 , H05K1/111 , H05K1/189 , H05K3/025 , H05K3/243 , H05K3/28 , H05K3/382 , H05K3/4007 , H05K2201/0367 , H05K2201/10674 , Y02P70/611
摘要： A wiring board includes: a flexible insulating base 1; a plurality of conductive wirings 2 arranged on the flexible insulating base 1; protruding electrodes 3 provided respectively at an end portion of the same side of each of the conductive wirings; external terminals 4, 5 formed respectively at the other end portions of each of the conductive wirings; metal plating layers applied on the conductive wirings, the protruding electrodes and the external terminals; and solder resist layers 7 formed respectively by coating the conductive wirings in regions between the end portions at which the protruding electrodes are provided and the external terminals. In the regions where the solder resist layers are formed, no metal plating layers are formed on the conductive wirings, and the surfaces of the conductive wirings to be contacted with the flexible insulating base are rougher than the surfaces not to be contacted with the flexible insulating base. Even when a film base is thin, bending stress applied to the conductive wirings is relieved sufficiently, and thus breaks in the wirings are suppressed.
摘要翻译：布线板包括：柔性绝缘基座1; 布置在柔性绝缘基座1上的多个导电布线2; 突出电极3分别设置在每个导电布线的同一侧的端部处; 外部端子4,5分别形成在每个导电布线的另一端部; 施加在导电布线，突出电极和外部端子上的金属镀层; 以及分别通过在设置有突出电极的端部与外部端子之间的区域中涂覆导电布线而形成的阻焊层7。在形成阻焊层的区域中，在导电布线上不形成金属镀层，与挠性绝缘基体接触的导电配线的表面比不与柔性绝缘体接触的表面更粗糙基础。即使当薄膜基底较薄时，施加到导电布线的弯曲应力被充分地减轻，因此抑制布线中断。

6. 发明授权

US07851904B2 Semiconductor device, method for manufacturing the same, and semiconductor device mounting structure 有权
标题翻译：半导体装置及其制造方法以及半导体装置安装结构
公开(公告)号：US07851904B2
公开(公告)日：2010-12-14
申请号：US11950625
申请日：2007-12-05
申请人： Yukihiro Kozaka , Yoshifumi Nakamura , Michinari Tetani
发明人： Yukihiro Kozaka , Yoshifumi Nakamura , Michinari Tetani
IPC分类号： H01L23/10 , H01L23/58
CPC分类号： H01L23/49572 , G02F1/13452 , H01L23/367 , H01L23/4006 , H01L24/12 , H01L24/50 , H01L24/75 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05655 , H01L2224/13144 , H01L2224/13155 , H01L2224/16 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/75 , H01L2224/75301 , H01L2224/81205 , H01L2224/81801 , H01L2224/81805 , H01L2224/81894 , H01L2224/81895 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the wiring board with the circuit forming region facing the opening, the electrode pad being connected electrically to the conductive wiring via a protruding electrode 3a; a sealing resin 7 that covers the connected portion between the electrode pad and the conductive wiring; a heat dissipating member 9 that is disposed so as to have a portion facing the opening; and a filling material 8 that has a heat conductivity higher than that of the sealing resin, and is filled into the opening, so as to be in contact with the circuit forming region of the semiconductor element and the heat dissipating member. Even when the wiring board has a small area, heat dissipation efficiency can be ensured, and low cost manufacture can be achieved.
摘要翻译：本发明的半导体器件包括：布线基板4，在具有开口部5a的绝缘基板5上形成导电布线6; 具有电路形成区域2a和电极焊盘3的半导体元件2，并且安装在布线板上，电路形成区域面向开口，电极焊盘通过突出电极3a与导电布线电连接; 覆盖电极焊盘和导电布线之间的连接部分的密封树脂7; 散热构件9，其布置成具有面向开口的部分; 以及填充材料8，其具有比密封树脂的热导率高的热导率，并且填充到开口中，以便与半导体元件的电路形成区域和散热构件接触。即使布线板面积小，也能够确保散热效率，能够实现低成本的制造。

7. 发明授权

US07514802B2 Wiring board 有权
标题翻译：接线板
公开(公告)号：US07514802B2
公开(公告)日：2009-04-07
申请号：US11531381
申请日：2006-09-13
申请人： Michinari Tetani , Takayuki Tanaka , Hiroyuki Imamura , Nozomi Shimoishizaka , Kouichi Nagao
发明人： Michinari Tetani , Takayuki Tanaka , Hiroyuki Imamura , Nozomi Shimoishizaka , Kouichi Nagao
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L23/4985 , H01L24/81 , H01L2223/5442 , H01L2223/54473 , H01L2224/81121 , H01L2224/81192 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/0269 , H05K1/0393 , H05K3/0097 , H05K3/303 , H05K2201/0367 , H05K2201/09781 , H05K2201/09918 , H05K2201/10674 , H05K2203/1545 , H05K2203/166
摘要： A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode. It is possible to configure a wiring board having register marks capable of positioning electrode pads of a semiconductor chip with respect to bump electrodes with high accuracy.
摘要翻译：提供柔性绝缘基座，在柔性绝缘基座上对准的多个导体布线和分别设置在要放置半导体芯片的区域中的多个导体布线的端部中的凸起电极。通过将形成在半导体芯片上的电极焊盘接合到凸块电极，将半导体芯片安装在导体布线上。在导体布线上形成类似于导体布线的辅助导体布线设置在绝缘基底上，并且在辅助导体布线上设置类似于隆起电极形成的辅助凸起电极，使得形成在半导体芯片上的电极焊盘可以被注册通过相对于辅助凸起电极定位半导体芯片，相对于导体布线上的凸块电极。可以配置具有能够高精度地相对于凸块电极定位半导体芯片的电极焊盘的对准标记的布线板。

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