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1. 发明授权

US11636882B2 Integrated assemblies having shield lines between neighboring transistor active regions 有权
公开(公告)号：US11636882B2
公开(公告)日：2023-04-25
申请号：US16667289
申请日：2019-10-29
申请人： Micron Technology, Inc.
发明人： Marcello Mariani , Antonino Rigano
IPC分类号： G11C5/00 , H01L27/108 , G11C5/06 , G11C5/02
摘要： Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

2. 发明申请

US20220037533A1 Integrated Transistors Having Gate Material Passing Through a Pillar of Semiconductor Material, and Methods of Forming Integrated Transistors 有权
公开(公告)号：US20220037533A1
公开(公告)日：2022-02-03
申请号：US17502546
申请日：2021-10-15
申请人： Micron Technology, Inc.
发明人： Antonino Rigano , Marcello Mariani
IPC分类号： H01L29/786 , H01L29/66 , H01L27/11592 , H01L27/11507 , H01L27/11509 , H01L27/108 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , G11C11/22 , G11C11/408 , H01L21/28 , H01L27/1159
摘要： Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

3. 发明申请

US20180006087A1 METHOD FOR BASE CONTACT LAYOUT, SUCH AS FOR MEMORY 审中-公开
公开(公告)号：US20180006087A1
公开(公告)日：2018-01-04
申请号：US15691576
申请日：2017-08-30
申请人： Micron Technology, Inc.
发明人： Antonino Rigano , Fabio Pellizzer , Gianfranco Capetti
IPC分类号： H01L27/24 , H01L27/10 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/101 , H01L27/2463 , H01L45/06 , H01L45/1233
摘要： Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

4. 发明授权

US11049769B2 Self-aligned interconnection for integrated circuits 有权
公开(公告)号：US11049769B2
公开(公告)日：2021-06-29
申请号：US16111004
申请日：2018-08-23
申请人： Micron Technology, Inc.
发明人： Fabio Pellizzer , Antonino Rigano , Roberto Somaschini
IPC分类号： H01L21/768 , H01L45/00 , H01L27/24 , H01L23/522 , H01L21/033 , H01L21/311
摘要： Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

5. 发明申请

US20210036162A1 Integrated Transistors Having Gate Material Passing Through a Pillar of Semiconductor Material, and Methods of Forming Integrated Transistors 有权
公开(公告)号：US20210036162A1
公开(公告)日：2021-02-04
申请号：US16526074
申请日：2019-07-30
申请人： Micron Technology, Inc.
发明人： Antonino Rigano , Marcello Mariani
IPC分类号： H01L29/786 , H01L27/1159 , H01L27/11592 , H01L27/11507 , H01L27/11509 , H01L27/108 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , G11C11/22 , G11C11/408 , H01L21/28 , H01L29/66
摘要： Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

6. 发明授权

US09548447B2 Integrated memory and methods of forming repeating structures 有权
标题翻译：集成记忆和形成重复结构的方法
公开(公告)号：US09548447B2
公开(公告)日：2017-01-17
申请号：US14927316
申请日：2015-10-29
申请人： Micron Technology, Inc.
发明人： Antonino Rigano
IPC分类号： H01L29/06 , H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/1286 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1691
摘要： Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.
摘要翻译：一些实施例包括具有穿过多个节点的重复板阵列的集成存储器。阵列包括行和列。沿着各列和各行的板在彼此基本正交的两个取向之间交替。一些实施方案包括形成重复结构的方法。形成图案，其包括相交的波浪线的格子和围绕格子的盒子。该图案具有贯穿其中的多个开口。衬垫材料沿着开口的侧壁。衬垫材料和图案沿着与行方向大致正交的行方向和列方向切片。这种切片将衬垫材料细分成多个板。这些板在包括列和行的阵列内。沿着各列和各行的板在彼此基本正交的两个取向之间交替。

7. 发明授权

US09520554B2 Clamp elements for phase change memory arrays 有权
标题翻译：用于相变存储器阵列的钳位元件
公开(公告)号：US09520554B2
公开(公告)日：2016-12-13
申请号：US13783884
申请日：2013-03-04
申请人： Micron Technology, Inc.
发明人： Antonino Rigano , Fabio Pellizzer
IPC分类号： G11C11/00 , G11C11/36 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/1691 , G11C13/0004 , G11C13/0023 , G11C13/0038 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/12 , H01L45/124 , H01L45/128 , H01L45/143 , H01L45/144 , H01L45/16
摘要： Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.
摘要翻译：本文公开了夹紧元件，存储器，装置及其形成方法。示例性存储器可以包括存储器单元阵列和多个钳位元件。多个钳位元件的钳位元件可以包括相对于存储器单元阵列的位线或字线中的至少一个非正交形成的单元结构，并且可以被配置为控制相应位线的电压。

8. 发明申请

US20150295173A1 Integrated Memory and Methods of Forming Repeating Structures 有权
标题翻译：集成记忆和形成重复结构的方法
公开(公告)号：US20150295173A1
公开(公告)日：2015-10-15
申请号：US14250114
申请日：2014-04-10
申请人： Micron Technology, Inc.
发明人： Antonino Rigano
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/1286 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1691
摘要： Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.
摘要翻译：一些实施例包括具有穿过多个节点的重复板阵列的集成存储器。阵列包括行和列。沿着各列和各行的板在彼此基本正交的两个取向之间交替。一些实施方案包括形成重复结构的方法。形成图案，其包括相交的波浪线的格子和围绕格子的盒子。该图案具有贯穿其中的多个开口。衬垫材料沿着开口的侧壁。衬垫材料和图案沿着与行方向大致正交的行方向和列方向切片。这种切片将衬垫材料细分成多个板。这些板在包括列和行的阵列内。沿着各列和各行的板在彼此基本正交的两个取向之间交替。

9. 发明申请

US20140085973A1 METHOD, SYSTEM AND DEVICE FOR RECESSED CONTACT IN MEMORY ARRAY 有权
标题翻译：方法，用于存储阵列中的被接触的系统和装置
公开(公告)号：US20140085973A1
公开(公告)日：2014-03-27
申请号：US13624627
申请日：2012-09-21
申请人： MICRON TECHNOLOGY, INC.
发明人： Fabio Pellizzer , Antonino Rigano , Marcello Mariani , Augusto Benvenuti
IPC分类号： H01L21/768 , H01L27/24 , G11C11/00 , H01L21/762
CPC分类号： H01L27/2445 , G11C13/0004 , H01L21/3086 , H01L21/762 , H01L27/2463 , H01L29/42304 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1675
摘要： Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
摘要翻译：本文公开的实施例可以涉及在存储器件中形成用于选择器晶体管和字线电极之间的互连的接触区域。

10. 发明授权

US11476304B2 Phase change memory device with voltage control elements 有权
公开(公告)号：US11476304B2
公开(公告)日：2022-10-18
申请号：US15375976
申请日：2016-12-12
申请人： MICRON TECHNOLOGY, INC.
发明人： Fabio Pellizzer , Antonino Rigano
IPC分类号： H01L45/00 , H01L27/24 , H01L27/02 , G11C13/00
摘要： A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

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