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    • 4. 发明授权
    • Operating memory with specified cache address
    • 具有指定缓存地址的操作内存
    • US08850119B2
    • 2014-09-30
    • US13867897
    • 2013-04-22
    • Micron Technology, Inc.
    • Theodore T. PeknyJeff Yu
    • G06F12/02G06F12/08
    • G06F12/0246G06F12/0804
    • Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host.
    • 提供的实施例用于通过向指定要发生操作的高速缓存和/或存储器阵列地址的存储器件发出某些指令来操作存储器件。 一种这样的方法可以包括将数据加载到存储器设备的高速缓存的指定地址中,其中存储器设备的高速缓存的指定地址可以由存储器设备的接口从主机接收的第一程序序列指定 外部存储器件。 该方法还可以包括将数据从存储器件的高速缓存的指定地址写入存储器件的存储器阵列的指定地址,其中存储器件的存储器阵列的指定地址可由 在主机的接口处接收到第二个程序序列。
    • 5. 发明申请
    • SERIAL INTERFACE NAND
    • 串行接口NAND
    • US20130238846A1
    • 2013-09-12
    • US13867897
    • 2013-04-22
    • MICRON TECHNOLOGY, INC.
    • Theodore T. PeknyJeff Yu
    • G06F12/02
    • G06F12/0246G06F12/0804
    • Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host.
    • 提供的实施例用于通过向指定要发生操作的高速缓存和/或存储器阵列地址的存储器件发出某些指令来操作存储器件。 一种这样的方法可以包括将数据加载到存储器设备的高速缓存的指定地址中,其中存储器设备的高速缓存的指定地址可以由存储器设备的接口从主机接收的第一程序序列指定 外部存储器件。 该方法还可以包括将数据从存储器件的高速缓存的指定地址写入存储器件的存储器阵列的指定地址,其中存储器件的存储器阵列的指定地址可由 在主机的接口处接收到第二个程序序列。