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1. 发明授权

US09318198B2 Memory system and method of operating the same 有权
标题翻译：内存系统及其操作方法
公开(公告)号：US09318198B2
公开(公告)日：2016-04-19
申请号：US13280860
申请日：2011-10-25
申请人： Min Joong Jung , Jung Mi Shin , Wan Seob Lee
发明人： Min Joong Jung , Wan Seob Lee
IPC分类号： G06F13/00 , G06F13/28 , G11C16/04 , G11C29/00
CPC分类号： G11C16/0483 , G11C29/82
摘要： A method of operating a memory system according to an aspect of the present disclosure includes storing first data in a memory controller; storing second data in the memory controller, wherein the second data is read from a selected page of a first memory block of a memory device; and performing a program operation for storing third data, that include the first data and the second data, in a selected page of a second memory block of the memory device.
摘要翻译：根据本公开的一个方面的操作存储器系统的方法包括将第一数据存储在存储器控制器中; 将第二数据存储在存储器控制器中，其中从存储器件的第一存储器块的选定页面读取第二数据; 以及执行用于将包括第一数据和第二数据的第三数据存储在存储器件的第二存储器块的选定页面中的程序操作。

2. 发明申请

US20120281488A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATION THE SAME 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20120281488A1
公开(公告)日：2012-11-08
申请号：US13286595
申请日：2011-11-01
申请人： Min Joong Jung , Wan Seob Lee , Jung Mi Shin
发明人： Min Joong Jung , Wan Seob Lee , Jung Mi Shin
IPC分类号： G11C7/10 , H03K17/00
CPC分类号： G11C7/1006
摘要： A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.
摘要翻译：半导体存储器件包括第一平面和第二平面，每个第一平面和第二平面被配置为包括多个存储单元，以及数据传输电路，被配置为将存储在第一平面的存储单元中的第一数据传送到第二平面并传送第二平面存储在第二平面的存储单元中的数据在进行复印操作时到第一平面，并且当执行读取操作时将第一数据或第二数据传送到I / O电路。

3. 发明授权

US08625376B2 Semiconductor memory device and method of operation the same 失效
标题翻译：半导体存储器件及其操作方法相同
公开(公告)号：US08625376B2
公开(公告)日：2014-01-07
申请号：US13286595
申请日：2011-11-01
申请人： Wan Seob Lee , Jung Mi Shin
发明人： Min Joong Jung , Wan Seob Lee
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1006
摘要： A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.
摘要翻译：半导体存储器件包括第一平面和第二平面，每个第一平面和第二平面被配置为包括多个存储单元，以及数据传输电路，被配置为将存储在第一平面的存储单元中的第一数据传送到第二平面并传送第二平面存储在第二平面的存储单元中的数据在进行复印操作时到第一平面，并且当执行读取操作时将第一数据或第二数据传送到I / O电路。

4. 发明申请

US20120163092A1 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US20120163092A1
公开(公告)日：2012-06-28
申请号：US13244217
申请日：2011-09-23
申请人： Min Joong Jung , Jung Mi Shin , Seong Je Park
发明人： Min Joong Jung , Jung Mi Shin , Seong Je Park
IPC分类号： G11C16/10
CPC分类号： G11C16/3454 , G11C16/10 , G11C16/3418
摘要： The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.
摘要翻译：非易失性存储器件的编程方法包括在增量步进脉冲程序（ISPP）方法的编程操作中检测对应于编程电压的增量的温度，设定阶梯电压，其中阶跃电压基于检测到的温度而改变，并且基于设定的步进电压执行编程操作和程序验证操作。

5. 发明授权

US08897066B2 Method of programming nonvolatile memory device 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US08897066B2
公开(公告)日：2014-11-25
申请号：US13340391
申请日：2011-12-29
申请人： Min Joong Jung
发明人： Min Joong Jung
IPC分类号： G11C16/06 , G11C16/10 , G11C16/04 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n−1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n−1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.
摘要翻译：一种对非易失性存储器件进行编程的方法包括响应于第一程序命令顺序地对存储器块的第一存储器块的所有物理页的第一至第（n-1）个逻辑页进行编程，第一至第（n-1）个逻辑页面，分别存储在第一存储器块的第一物理页面中，并且当接收到第二程序时，分别将加载的数据锁存在每个页缓冲器的第一至第（n-1）个锁存器中在第一至第（n-1）个逻辑页面进行编程之后，将与第二程序命令一起接收的新程序数据锁存在相应的页缓冲器的第n个锁存器中，并对第一至第n个存储的数据进行编程页面缓冲器的锁存器插入到存储器块的第二存储器块的第一物理页面中。

6. 发明授权

US07684254B2 Flash memory device and method of erasing memory cell block in the same 有权
标题翻译：闪存器件和擦除存储单元块的方法相同
公开(公告)号：US07684254B2
公开(公告)日：2010-03-23
申请号：US11617670
申请日：2006-12-28
申请人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
发明人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , H01L2924/0002 , H01L2924/00
摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.
摘要翻译：闪存器件包括具有多个块的存储单元阵列。地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号。控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。

7. 发明申请

US20080084766A1 FLASH MEMORY DEVICE AND METHOD OF ERASING MEMORY CELL BLOCK IN THE SAME 有权
标题翻译：闪存存储器件及其中存储单元块的擦除方法
公开(公告)号：US20080084766A1
公开(公告)日：2008-04-10
申请号：US11617670
申请日：2006-12-28
申请人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
发明人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , H01L2924/0002 , H01L2924/00
摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.
摘要翻译：闪存器件包括具有多个块的存储单元阵列。地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号。控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。

8. 发明授权

US08107287B2 Method of programming nonvolatile memory device 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US08107287B2
公开(公告)日：2012-01-31
申请号：US12695525
申请日：2010-01-28
申请人： Min Joong Jung
发明人： Min Joong Jung
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n−1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n−1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.
摘要翻译：一种对非易失性存储器件进行编程的方法包括响应于第一程序命令顺序地对存储器块的第一存储器块的所有物理页的第一至第（n-1）个逻辑页进行编程，第一至第（n-1）个逻辑页面，分别存储在第一存储器块的第一物理页面中，并且当接收到第二程序时，分别将加载的数据锁存在每个页缓冲器的第一至第（n-1）个锁存器中在第一至第（n-1）个逻辑页面进行编程之后，将与第二程序命令一起接收的新程序数据锁存在相应的页缓冲器的第n个锁存器中，并对第一至第n个存储的数据进行编程页面缓冲器的锁存器插入到存储器块的第二存储器块的第一物理页面中。

9. 发明授权

US08717821B2 Nonvolatile memory device and method of programming the same 有权
标题翻译：非易失存储器件及其编程方法
公开(公告)号：US08717821B2
公开(公告)日：2014-05-06
申请号：US13244217
申请日：2011-09-23
申请人： Seong Je Park , Jung Mi Shin
发明人： Min Joong Jung , Seong Je Park
IPC分类号： G11C16/04
CPC分类号： G11C16/3454 , G11C16/10 , G11C16/3418
摘要： The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.
摘要翻译：非易失性存储器件的编程方法包括在增量步进脉冲程序（ISPP）方法的编程操作中检测对应于编程电压的增量的温度，设定阶梯电压，其中阶跃电压基于检测到的温度而改变，并且基于设定的步进电压执行编程操作和程序验证操作。

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