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1. 发明授权

US08772105B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08772105B2
公开(公告)日：2014-07-08
申请号：US13211249
申请日：2011-08-16
申请人： Tae Su Jang , Min Soo Yoo
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L21/8242
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括形成在垂直柱的底部的第一结区域，形成在第一结区下方的位线，以及形成在位线下方的绝缘膜。结果，提供4F2尺寸的半导体器件，并且位线被配置为导电层和多晶硅层的叠层结构的形式，使得位线电阻降低。此外，半导体器件通过在导电层和多晶硅层之间形成硅化物来降低欧姆接触电阻，并且在半导体衬底和位线之间的位置处包括绝缘膜，导致位线电容降低。因此，半导体器件的感测裕度增加，并且数据保持时间也增加。

2. 发明授权

US08004048B2 Semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage (GIDL) and method for manufacturing the same 失效
标题翻译：具有能够实现栅极引起的漏极泄漏（GIDL）的降低的掩埋栅极的半导体器件及其制造方法
公开(公告)号：US08004048B2
公开(公告)日：2011-08-23
申请号：US12493268
申请日：2009-06-29
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4236 , H01L21/28238 , H01L29/66553 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage is presented. The semiconductor device includes a semiconductor substrate, a buried gate, and a barrier layer. The semiconductor substrate has a groove. The buried gate is formed in a lower portion of the groove and has a lower portion wider than an upper portion. The barrier layer is formed on sidewalls of the upper portion of the buried gate.
摘要翻译：提出了具有能够实现栅极引起漏极漏极减少的掩埋栅极的半导体器件。半导体器件包括半导体衬底，掩埋栅极和阻挡层。半导体衬底具有凹槽。掩埋栅极形成在槽的下部，并且具有比上部更宽的下部。阻挡层形成在掩埋栅极的上部的侧壁上。

3. 发明授权

US07378307B2 Gate of a semiconductor device and method for forming the same 失效
标题翻译：半导体器件的栅极及其形成方法
公开(公告)号：US07378307B2
公开(公告)日：2008-05-27
申请号：US11458224
申请日：2006-07-18
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L21/8238
CPC分类号： H01L29/0653 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having the SiGe film formed thereon, selectively etching the SiGe film, embedding a dielectric material into a portion where the SiGe film is removed, forming a stepped profile on the silicon film by etching a predetermined portion of the silicon film such that the bit-line node portion is included in the stepped profile, and forming a gate on the silicon film having the stepped profile formed therein such that the gate overlaps the stepped profile. The dielectric pad prevents the bit-line junction from spreading downward upon operation of the gate, thereby enhancing a punch-through phenomenon.
摘要翻译：这里公开了一种在半导体器件中形成栅极结构的方法。该方法包括在对应于形成位线结的位线节点部分的硅衬底的预定区域上形成SiGe膜，在其上形成有SiGe膜的硅衬底上生长硅膜，选择性地蚀刻 SiGe膜，将介电材料嵌入到去除SiGe膜的部分中，通过蚀刻硅膜的预定部分使得在硅膜上形成阶梯形轮廓，使得位线节点部分包括在阶梯轮廓中，以及在硅膜上形成具有形成在其中的阶梯轮廓的栅极，使得栅极与阶梯轮廓重叠。电介质垫在栅极操作时防止位线结面向下扩展，从而增强穿通现象。

4. 发明授权

US07927962B2 Semiconductor device having buried insulation films and method of manufacturing the same 失效
标题翻译：具有掩埋绝缘膜的半导体器件及其制造方法
公开(公告)号：US07927962B2
公开(公告)日：2011-04-19
申请号：US12399683
申请日：2009-03-06
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L21/76
CPC分类号： H01L27/10802 , H01L21/76264 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/1203
摘要： A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a second trench in the first direction; and (h) forming device isolation films in the first and second trenches.
摘要翻译：一种通过该方法制造半导体器件和半导体器件的方法，所述方法包括：（a）在半导体衬底上形成缓冲层; （b）沿第一方向图案化缓冲层以形成具有侧表面并以预定间隔彼此间隔的缓冲层图案; （c）在缓冲层图案之间和之间形成半导体外延层; （d）在垂直于第一方向的第二方向上在半导体外延层中形成第一沟槽以暴露缓冲层图案的侧表面; （e）选择性地去除由第一沟槽露出的缓冲层图案以形成空间; （f）在通过去除缓冲层图案形成的空间中形成掩埋绝缘膜，半导体外延层的一部分设置在掩埋绝缘膜之间; （g）去除设置在掩埋绝缘膜之间的半导体外延层的一部分，以在第一方向上形成第二沟槽; 和（h）在第一和第二沟槽中形成器件隔离膜。

5. 发明授权

US07102187B2 Gate structure of a semiconductor device 失效
标题翻译：半导体器件的栅极结构
公开(公告)号：US07102187B2
公开(公告)日：2006-09-05
申请号：US11174788
申请日：2005-07-05
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/0653 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having the SiGe film formed thereon, selectively etching the SiGe film, embedding a dielectric material into a portion where the SiGe film is removed, forming a stepped profile on the silicon film by etching a predetermined portion of the silicon film such that the bit-line node portion is included in the stepped profile, and forming a gate on the silicon film having the stepped profile formed therein such that the gate overlaps the stepped profile. The dielectric pad prevents the bit-line junction from spreading downward upon operation of the gate, thereby enhancing a punch-through phenomenon.
摘要翻译：这里公开了一种在半导体器件中形成栅极结构的方法。该方法包括在对应于形成位线结的位线节点部分的硅衬底的预定区域上形成SiGe膜，在其上形成有SiGe膜的硅衬底上生长硅膜，选择性地蚀刻 SiGe膜，将介电材料嵌入到去除SiGe膜的部分中，通过蚀刻硅膜的预定部分使得在硅膜上形成阶梯形轮廓，使得位线节点部分包括在阶梯轮廓中，以及在硅膜上形成具有形成在其中的阶梯轮廓的栅极，使得栅极与阶梯轮廓重叠。电介质垫在栅极操作时防止位线结面向下扩展，从而增强穿通现象。

6. 发明授权

US09196618B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09196618B2
公开(公告)日：2015-11-24
申请号：US13290745
申请日：2011-11-07
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L29/78 , H01L27/108 , H01L21/768 , H01L21/762
CPC分类号： H01L27/10855 , H01L21/76224 , H01L21/76801 , H01L21/76897 , H01L27/10814 , H01L27/10876
摘要： A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.
摘要翻译：提供一种半导体器件及其制造方法，其中增加了存储节点接触和有源区域之间的完全重叠以解决蚀刻工艺中的覆盖和存储节点的蚀刻宽度，以提高处理裕度。半导体器件包括设置在半导体器件中的主栅极和器件隔离结构，设置在器件隔离结构上的隔离图案，以及设置在隔离图案的每一侧的接触插塞。

7. 发明授权

US08420484B2 Semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage (GIDL) and method for manufacturing the same 有权
标题翻译：具有能够实现栅极引起的漏极泄漏（GIDL）的降低的掩埋栅极的半导体器件及其制造方法
公开(公告)号：US08420484B2
公开(公告)日：2013-04-16
申请号：US13184887
申请日：2011-07-18
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L21/28238 , H01L29/66553 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage is presented. The semiconductor device includes a semiconductor substrate, a buried gate, and a barrier layer. The semiconductor substrate has a groove. The buried gate is formed in a lower portion of the groove and has a lower portion wider than an upper portion. The barrier layer is formed on sidewalls of the upper portion of the buried gate.
摘要翻译：提出了具有能够实现栅极引起的漏极泄漏减小的掩埋栅极的半导体器件。半导体器件包括半导体衬底，掩埋栅极和阻挡层。半导体衬底具有凹槽。掩埋栅极形成在槽的下部，并且具有比上部更宽的下部。阻挡层形成在掩埋栅极的上部的侧壁上。

8. 发明申请

US20100096701A1 Semiconductor Device and Method of Manufacturing the Same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100096701A1
公开(公告)日：2010-04-22
申请号：US12399683
申请日：2009-03-06
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L29/772 , H01L21/762
CPC分类号： H01L27/10802 , H01L21/76264 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/1203
摘要： A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a second trench in the first direction; and (h) forming device isolation films in the first and second trenches.
摘要翻译：一种通过该方法制造半导体器件和半导体器件的方法，所述方法包括：（a）在半导体衬底上形成缓冲层; （b）沿第一方向图案化缓冲层以形成具有侧表面并以预定间隔彼此间隔的缓冲层图案; （c）在缓冲层图案之间和之间形成半导体外延层; （d）在垂直于第一方向的第二方向上在半导体外延层中形成第一沟槽以暴露缓冲层图案的侧表面; （e）选择性地去除由第一沟槽露出的缓冲层图案以形成空间; （f）在通过去除缓冲层图案形成的空间中形成掩埋绝缘膜，半导体外延层的一部分设置在掩埋绝缘膜之间; （g）去除设置在掩埋绝缘膜之间的半导体外延层的一部分，以在第一方向上形成第二沟槽; 和（h）在第一和第二沟槽中形成器件隔离膜。

9. 发明申请

US20120168854A1 SEMICONDUCTOR DEVICE AND METOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168854A1
公开(公告)日：2012-07-05
申请号：US13211249
申请日：2011-08-16
申请人： Tae Su JANG , Min Soo Yoo
发明人： Tae Su JANG , Min Soo Yoo
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括形成在垂直柱的底部的第一结区域，形成在第一结区下方的位线，以及形成在位线下方的绝缘膜。结果，提供4F2尺寸的半导体器件，并且位线被配置为导电层和多晶硅层的叠层结构的形式，使得位线电阻降低。此外，半导体器件通过在导电层和多晶硅层之间形成硅化物来降低欧姆接触电阻，并且在半导体衬底和位线之间的位置处包括绝缘膜，导致位线电容降低。因此，半导体器件的感测裕度增加，并且数据保持时间也增加。

10. 发明申请

US20110180873A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110180873A1
公开(公告)日：2011-07-28
申请号：US13081286
申请日：2011-04-06
申请人： Min Soo Yoo
发明人： Min Soo Yoo
IPC分类号： H01L29/78
CPC分类号： H01L21/76264 , H01L21/84 , H01L27/10802 , H01L27/10894 , H01L27/1207 , H01L29/7841
摘要： The invention also provides a semiconductor device comprising: a plurality of first gate patterns disposed in a cell area of a substrate region; a plurality of first junction regions disposed in the cell area respectively adjacent to the first gate patterns; buried insulation film buried in the middle area of the substrate region at a bottom region of the cell area; at least one second gate pattern disposed in a peripheral area of the substrate region; and a plurality of second junction regions disposed in the substrate region respectively adjacent to the second gate pattern.
摘要翻译：本发明还提供了一种半导体器件，包括：设置在衬底区域的单元区域中的多个第一栅极图案; 多个第一结区域，分别设置在与所述第一栅极图案相邻的所述单元区域中; 掩埋绝缘膜埋在基板区域的中部区域的底部区域; 设置在所述基板区域的周边区域中的至少一个第二栅极图案; 以及多个第二连接区域，分别设置在与第二栅极图案相邻的基板区域中。

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