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    • 7. 发明申请
    • Semiconductor memory device for reducing precharge time
    • 用于减少预充电时间的半导体存储器件
    • US20080310243A1
    • 2008-12-18
    • US12155885
    • 2008-06-11
    • Jong-hoon JungGyu-hong Kim
    • Jong-hoon JungGyu-hong Kim
    • G11C7/00
    • G11C7/12
    • A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.
    • 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器,预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元,并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。
    • 8. 发明授权
    • Semiconductor integrated circuit, method of designing the same, and method of fabricating the same
    • 半导体集成电路及其设计方法及其制造方法
    • US09026975B2
    • 2015-05-05
    • US13800483
    • 2013-03-13
    • Tae-joong SongPil-un KoGyu-hong KimJong-hoon Jung
    • Tae-joong SongPil-un KoGyu-hong KimJong-hoon Jung
    • G06F17/50H01L27/092H01L27/02
    • G06F17/5072G06F17/50G06F17/5077G06F17/5081H01L27/0207H01L27/092H01L27/0924H01L29/6681
    • A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.
    • 提供了一种半导体集成电路设计方法及其制造方法,该方法能够最小化由导线,特别是栅极线,半导体集成电路中的开销产生的寄生电容及其制造方法。 一种设计具有FinFET架构的半导体集成电路的方法,包括:对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局,所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域,以使由第一切割区域产生的第一导电线路的开销最小化。