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    • 1. 发明申请
    • METHOD FOR WAFER ANALYSIS WITH ARTIFICIAL NEURAL NETWORK AND SYSTEM THEREOF
    • 用人造神经网络进行波浪分析的方法及其系统
    • US20080301073A1
    • 2008-12-04
    • US11872414
    • 2007-10-15
    • Ming-Chin TSAI
    • Ming-Chin TSAI
    • G06F15/18
    • G06N3/02
    • A method for wafer analysis with artificial neural network and the system thereof are disclosed. The method of the system of the present invention has several steps, including: first of all, providing a test unit for wafer test and generating a plurality of test data; next, transmitting the test data to a processing unit for transferring to output data; then, comparing the output data with predictive value and modifying bias and making the output data close to the predictive value, and repeating the steps mentioned above to train this system; finally, analyzing wafers by the trained system. Using this system to analyze wafers not only saves time, but also reduces manpower and the risk resulting from artificial analysis.
    • 公开了一种使用人造神经网络进行晶片分析的方法及其系统。 本发明的系统的方法具有以下几个步骤:首先,提供用于晶片测试的测试单元并产生多个测试数据; 接下来,将测试数据发送到处理单元以传送到输出数据; 然后,将输出数据与预测值进行比较,并修改偏差,使输出数据接近预测值,并重复上述步骤对该系统进行训练; 最后,通过训练有素的系统分析晶片。 使用该系统分析晶圆不仅可以节省时间,还可以减少人力和人为分析造成的风险。
    • 2. 发明申请
    • Method for Disposing Power/Ground Plane of PCB
    • PCB布置电源/接地面的方法
    • US20100030513A1
    • 2010-02-04
    • US12329730
    • 2008-12-08
    • Ming-Chin TSAI
    • Ming-Chin TSAI
    • G01B21/00G06F15/00
    • H05K3/0005H05K1/0262H05K1/115H05K2201/093H05K2201/09663
    • A method for disposing power planes and ground planes of a printed circuit board (PCB), said method comprising the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on said PCB for intersecting said geometric layout to form a plurality of points of intersection; defining line segments by segmenting said line at each of said points of intersection to form a plurality of line segments; deleting some of said line segments having one end not being point of intersection for said geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in said plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within said smallest closed region.
    • 一种用于布置印刷电路板(PCB)的电源平面和接地平面的方法,所述方法包括以下步骤:提供PCB,其上布置有几何布局和通孔; 在所述PCB上提供一条线,用于与所述几何布局相交以形成多个交点; 通过在每个所述交叉点处分割所述线来形成多个线段来定义线段; 删除一些所述线段,其一端不是所述几何布局的交点,以形成多个分段区域; 通过从所述多个分割区域中的任何一个点反复搜索区域来搜索封闭区域; 确定封闭区域是否是最小的封闭区域; 确定通孔是否位于所述最小封闭区域内。
    • 4. 发明申请
    • METHOD FOR STACKED PATTERN DESIGN OF PRINTED CIRCUIT BOARD AND SYSTEM THEREOF
    • 印刷电路板的堆叠图案设计方法及其系统
    • US20090031273A1
    • 2009-01-29
    • US11970744
    • 2008-01-08
    • Ming-Chin TSAI
    • Ming-Chin TSAI
    • G06F17/50
    • G06N3/126G06F17/5068H05K3/0005H05K3/4611H05K2201/0352H05K2201/09736
    • A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked pattern is inputted into operational interface of the software; Next, initial solution sets of stacked pattern are generated; Then, duplications of the initial solution sets of stacked pattern are generated according to a fitness function; Afterward, crossover of the duplications of stacked pattern are performed at random; Then, mutations are executed by a probability at random; Finally, identification is performed to check if the solution approaches the standard of demand and the result of stacked pattern is shown; otherwise, operational step jumps to duplicate step and repeats above steps until satisfying solution is obtained. The most suitable way for package can be arranged out through making especially mathematical calculations by the system efficiently.
    • 公开了一种利用遗传算法设计PCB堆叠图案的方法及其系统。 该方法包括以下步骤:首先将堆叠模式的信息数据输入软件的操作界面; 接下来,生成堆叠图案的初始解集; 然后,根据适应度函数生成堆叠模式的初始解集的重复; 之后,堆叠图案的重复的交叉随机进行; 然后,以概率随机地执行突变; 最后,进行识别以检查解决方案是否接近需求标准,并显示堆叠模式的结果; 否则,操作步骤跳转到重复步骤,重复上述步骤,直到获得满足的解。 最合适的包装方式可以通过系统进行特别的数学计算来排除。
    • 6. 发明申请
    • METHOD AND APPARATUS FOR DETERMINING DISPOSITION OF VIA HOLE ON PRINTED CIRCUIT BOARD
    • 用于确定打印电路板上孔的处理的方法和装置
    • US20120041710A1
    • 2012-02-16
    • US13233121
    • 2011-09-15
    • Ming-Chin TSAI
    • Ming-Chin TSAI
    • G06F15/00
    • H05K3/0005H05K1/0262H05K1/115H05K2201/093H05K2201/09663
    • A method for determining disposition of via hole on printed circuit board (PCB), said method comprising the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on said PCB for intersecting said geometric layout to form a plurality of points of intersection; defining line segments by segmenting said line at each of said points of intersection to form a plurality of line segments; deleting some of said line segments having one end not being point of intersection for said geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in said plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within said smallest closed region.
    • 一种用于确定印刷电路板(PCB)上的通孔的配置的方法,所述方法包括以下步骤:提供PCB,其上布置有几何布局和通孔; 在所述PCB上提供一条线,用于与所述几何布局相交以形成多个交点; 通过在每个所述交叉点处分割所述线来形成多个线段来定义线段; 删除一些所述线段,其一端不是所述几何布局的交点,以形成多个分段区域; 通过从所述多个分割区域中的任何一个点反复搜索区域来搜索封闭区域; 确定封闭区域是否是最小的封闭区域; 确定通孔是否位于所述最小封闭区域内。