会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Finite element modeling method utilizing mass distribution
    • 利用质量分布的有限元建模方法
    • US20070282571A1
    • 2007-12-06
    • US11444281
    • 2006-05-30
    • Mostafa RassaianDavid W. TwiggJeffrey Ko
    • Mostafa RassaianDavid W. TwiggJeffrey Ko
    • G06F17/10
    • G06F17/5018G06F17/5095
    • The invention discloses differing embodiments of finite element modeling methods utilizing mass distribution to model an object. In one embodiment, the finite element model of the object may be partitioned into sub-models. A determination may be made as to which elements in the finite element model are structural and as to which elements in the finite element model are non-structural. Mass properties for both the structural and non-structural elements in each sub-model may be determined. The significant non-structural masses within each sub-model may be selected and added to the finite element model. The remaining insignificant, non-structural masses may be incorporated onto the structural masses by scaling densities of the structural masses. The scaled structural masses may then be added to the finite element model. In other embodiments, objects are provided which were modeled utilizing finite element models under the invention.
    • 本发明公开了利用质量分布来建模物体的有限元建模方法的不同实施例。 在一个实施例中,对象的有限元模型可以被划分为子模型。 可以确定有限元模型中的哪些元素是结构性的,以及有限元模型中的哪些元素是非结构的。 可以确定每个子模型中的结构元件和非结构元件的质量特性。 每个子模型中的重要非结构质量可以被选择并添加到有限元模型中。 剩余的微不足道的非结构物质可以通过结构物质的结垢密度掺入到结构物质中。 然后可以将缩放的结构质量添加到有限元模型中。 在其它实施例中,提供了利用本发明的有限元模型来建模的对象。
    • 2. 发明授权
    • Finite element modeling method utilizing mass distribution
    • 利用质量分布的有限元建模方法
    • US07840386B2
    • 2010-11-23
    • US11444281
    • 2006-05-30
    • Mostafa RassaianDavid W. TwiggJeffrey Ko
    • Mostafa RassaianDavid W. TwiggJeffrey Ko
    • G06F17/50
    • G06F17/5018G06F17/5095
    • The invention discloses differing embodiments of finite element modeling methods utilizing mass distribution to model an object. In one embodiment, the finite element model of the object may be partitioned into sub-models. A determination may be made as to which elements in the finite element model are structural and as to which elements in the finite element model are non-structural. Mass properties for both the structural and non-structural elements in each sub-model may be determined. The significant non-structural masses within each sub-model may be selected and added to the finite element model. The remaining insignificant, non-structural masses may be incorporated onto the structural masses by scaling densities of the structural masses. The scaled structural masses may then be added to the finite element model. In other embodiments, objects are provided which were modeled utilizing finite element models under the invention.
    • 本发明公开了利用质量分布来建模物体的有限元建模方法的不同实施例。 在一个实施例中,对象的有限元模型可以被划分为子模型。 可以确定有限元模型中的哪些元素是结构性的,以及有限元模型中的哪些元素是非结构的。 可以确定每个子模型中的结构元件和非结构元件的质量特性。 每个子模型中的重要非结构质量可以被选择并添加到有限元模型中。 剩余的微不足道的非结构物质可以通过结构物质的结垢密度掺入到结构物质中。 然后可以将缩放的结构质量添加到有限元模型中。 在其它实施例中,提供了利用本发明的有限元模型来建模的对象。
    • 3. 发明申请
    • METHOD AND APPARATUS FOR INTEGRATED HIERARCHICAL ELECTRONICS ANALYSIS
    • 综合分层电子分析方法与装置
    • US20080104553A1
    • 2008-05-01
    • US11549819
    • 2006-10-16
    • Mostafa RassaianDavid W. TwiggJung-Chuan Lee
    • Mostafa RassaianDavid W. TwiggJung-Chuan Lee
    • G06F17/50
    • G06F17/50G06F17/5018G06F17/5095G06F2217/80H05K3/341
    • A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis and include the electronic components. The finite element model for the chassis is combined with the set of finite element models to form a combined finite element model. A finite element analysis of the combined finite element model is performed to form results. The combined model results are transferred to the printed wiring board models. Using the transferred results, stresses and strains are calculated for individual solder joints/leads. A fatigue analysis is performed for the electronic components in the set of printed wiring assemblies based on these stresses and strains, using the results to identify the durability of the electronic components.
    • 一种用于分析电子部件的耐久性的计算机实现的方法,装置和计算机可用程序代码。 创建了底盘的有限元模型。 创建了一组用于一组印刷线路组件的有限元模型,其中印刷线路组件用于底盘并且包括电子部件。 底盘的有限元模型与有限元模型组合形成一个组合有限元模型。 进行组合有限元模型的有限元分析,形成结果。 组合的模型结果转移到印刷线路板型号。 使用转移的结果,计算各个焊点/引线的应力和应变。 基于这些应力和应变,对印刷布线组件中的电子部件进行疲劳分析,结果确定电子部件的耐久性。
    • 5. 发明授权
    • Method and apparatus for integrated hierarchical electronics analysis
    • 集成分层电子分析的方法和装置
    • US07558639B2
    • 2009-07-07
    • US11549819
    • 2006-10-16
    • Mostafa RassaianDavid W. TwiggJung-Chuan Lee
    • Mostafa RassaianDavid W. TwiggJung-Chuan Lee
    • G06F17/50G06F19/00
    • G06F17/50G06F17/5018G06F17/5095G06F2217/80H05K3/341
    • A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis and include the electronic components. The finite element model for the chassis is combined with the set of finite element models to form a combined finite element model. A finite element analysis of the combined finite element model is performed to form results. The combined model results are transferred to the printed wiring board models. Using the transferred results, stresses and strains are calculated for individual solder joints/leads. A fatigue analysis is performed for the electronic components in the set of printed wiring assemblies based on these stresses and strains, using the results to identify the durability of the electronic components.
    • 一种用于分析电子部件的耐久性的计算机实现的方法,装置和计算机可用程序代码。 创建了底盘的有限元模型。 创建了一组用于一组印刷线路组件的有限元模型,其中印刷线路组件用于底盘并且包括电子部件。 底盘的有限元模型与有限元模型组合形成一个组合有限元模型。 进行组合有限元模型的有限元分析,形成结果。 组合的模型结果转移到印刷线路板型号。 使用转移的结果,计算各个焊点/引线的应力和应变。 基于这些应力和应变,对印刷布线组件中的电子部件进行疲劳分析,结果确定电子部件的耐久性。
    • 9. 发明授权
    • Method and apparatus for redundancy in an ATM using hot swap hardware underlying a virtual machine
    • 使用虚拟机下的热插拔硬件的ATM中的冗余的方法和装置
    • US08689039B1
    • 2014-04-01
    • US13015757
    • 2011-01-28
    • Nicholas J. MunsonDavid W. TwiggDaniel J. Farinella
    • Nicholas J. MunsonDavid W. TwiggDaniel J. Farinella
    • G09F11/00
    • G06F11/203G06F11/1402G06F2201/805G06F2201/815G07F19/20G07F19/211
    • A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. The hardware platform of the ATM is configured to tolerate removal of a portion of the hardware as well as insertion of a portion of the hardware without removing power from the ATM. The insertion and replacement of hardware to a powered device is termed a “hot swap”. A hot swap may be necessitated by the failure or the upgrade of a hardware component. The hot swap is detected by a software program running on top of the hardware platform. The software program may reintegrate the replacement hardware including the location of “drivers” for the replacement software. In addition, application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment.
    • 提供了一种在自动取款机(ATM)中提供冗余的方法和装置。 ATM的硬件平台被配置为容忍去除硬件的一部分以及插入硬件的一部分而不用从ATM中移除电力。 将硬件插入和更换到有源设备被称为“热插拔”。 硬件组件的故障或升级可能需要热插拔。 热插拔由在硬件平台上运行的软件程序来检测。 软件程序可能会重新整合替换硬件,包括替换软件的“驱动程序”位置。 此外,应用软件可以在诸如虚拟机和/或虚拟磁盘环境的虚拟环境之上运行。 如果软件组件出现故障,虚拟环境将“崩溃”,但ATM硬件和操作系统将保持不变。 如果软件存在致命的缺陷 - 例如,由于“升级”故障,旧版本可能会从以前存储的虚拟环境“回滚”。
    • 10. 发明授权
    • Apparatus and methods for maintenance task analysis
    • 维护任务分析的装置和方法
    • US07188051B2
    • 2007-03-06
    • US11196165
    • 2005-08-03
    • Michael A. MilletteDavid W. Twigg
    • Michael A. MilletteDavid W. Twigg
    • G06F3/023
    • G06Q10/06
    • A system for evaluating time requirements for performing maintenance on a maintenance object. One or more processors and memory are operable to provide a form on which a user describes a maintenance task. The described task is made available for maintenance time analysis as at least one of the following: a main task, a subtask of another main task, and an elementary operation. The user is allowed to combine a plurality of described tasks into one or more hierarchies designated by the user. This system provides flexibility to evaluate maintenance task times regardless of whether a level of detail and/or design maturity is minimal or complete.
    • 用于评估对维护对象进行维护的时间要求的系统。 一个或多个处理器和存储器可操作以提供用户描述维护任务的形式。 所描述的任务可用于以下至少一个维护时间分析:主任务,另一主要任务的子任务和基本操作。 允许用户将多个描述的任务组合成由用户指定的一个或多个层次结构。 该系统提供了评估维护任务时间的灵活性,而不管细节水平和/或设计成熟度是否最小化或完成。