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1. 发明授权

US08230373B2 ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device 有权
标题翻译：用于设计半导体器件的ESD分析器件和ESD分析程序以及设计半导体器件的方法
公开(公告)号：US08230373B2
公开(公告)日：2012-07-24
申请号：US12874782
申请日：2010-09-02
申请人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
发明人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.
摘要翻译：公开了ESD分析方法和计算机程序产品。执行包括第一电源焊盘，第二电源焊盘和第一电源焊盘和第二电源焊盘之间的多条电流路径的半导体集成电路的设计数据的电路仿真，以计算多个电源当在第一电源焊盘和第二电源焊盘之间施加ESD电流和ESD电压中的一个时，电流路径。通过基于所计算的电位计算耦合到第一电源焊盘的第一节点和耦合到第二电源焊盘的第二节点之间的电位差来检查ESD容限。当电位差低于预定值时，第一节点和第二节点被确定为要耦合到边界小区的节点。

2. 发明授权

US08125749B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US08125749B2
公开(公告)日：2012-02-28
申请号：US12929003
申请日：2010-12-22
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic protection circuit includes a first terminal, a second terminal, an input circuit which includes a Metal Oxide Semiconductor (MOS) transistor including a gate, a source, and a drain, the gate as an input terminal being coupled to the first terminal, the source being coupled to the second terminal, an electrostatic protection element connected to the drain, the electrostatic protection element including a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal.
摘要翻译：静电保护电路包括第一端子，第二端子，包括具有栅极，源极和漏极的金属氧化物半导体（MOS）晶体管的输入电路，栅极作为与第一端子耦合的输入端子，源极耦合到第二端子，连接到漏极的静电保护元件，静电保护元件包括第一静电保护元件，以及连接在第一端子和第二端子之间的第二静电保护元件。

3. 发明申请

US20110022376A1 ESD ANALYSIS DEVICE AND ESD ANALYSIS PROGRAM USED FOR DESIGNING SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE 有权
标题翻译：用于设计半导体器件的ESD分析器件和ESD分析程序及设计半导体器件的方法
公开(公告)号：US20110022376A1
公开(公告)日：2011-01-27
申请号：US12874782
申请日：2010-09-02
申请人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
发明人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.
摘要翻译： ESD（静电放电）分析装置包括：电路模拟单元; 边界细胞提取单元; 和支票单位。电路模拟单元执行包括多个电源系统的多个电路的半导体集成电路的设计数据的电路仿真，以计算多个电源系统中不同的两个电源系统的焊盘之间的多个电流路径中的电位当ESD垫片之间施加ESD电流和ESD电压之一时。边界单元提取单元从多个电源系统中的不同两个电路的电路中提取边界单元，其中电路包括在多个电路中，边界单元在电路之间输入和/或输出信号。检查单元通过基于所计算的电位，提取的边界单元计算边界单元之间的电势差来检查ESD容限。

4. 发明授权

US07859808B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US07859808B2
公开(公告)日：2010-12-28
申请号：US12149577
申请日：2008-05-05
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic protection circuit, includes a first terminal, a second terminal, a MOS transistor including a gate, a source, and a drain, the gate being coupled to the first terminal, the source being coupled to the second terminal, and an electrostatic protection element connected to the drain, wherein the electrostatic protection element includes a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal. The electrostatic protection circuit is constructed such that a maximum value of a voltage applied to a gate insulating film of the MOS transistor is alleviated to a value equal to or smaller than a desirable value by a current flowing into the first electrostatic protection element at a time of electrostatic application to the first terminal and an internal parasitic resistance of the MOS transistor connected with the second terminal.
摘要翻译：一种静电保护电路，包括第一端子，第二端子，包括栅极，源极和漏极的MOS晶体管，栅极耦合到第一端子，源极耦合到第二端子，以及静电保护元件连接到漏极，其中静电保护元件包括第一静电保护元件和连接在第一端子和第二端子之间的第二静电保护元件。静电保护电路被构造成使得通过每次流入第一静电保护元件的电流将施加到MOS晶体管的栅极绝缘膜的电压的最大值减轻到等于或小于期望值的值静电施加到第一端子以及与第二端子连接的MOS晶体管的内部寄生电阻。

5. 发明授权

US07853909B2 ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device 有权
标题翻译：用于设计半导体器件的ESD分析器件和ESD分析程序以及设计半导体器件的方法
公开(公告)号：US07853909B2
公开(公告)日：2010-12-14
申请号：US11905703
申请日：2007-10-03
申请人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
发明人： Susumu Kobayashi , Morihisa Hirata , Mototsugu Okushima , Tomohiro Kitayama , Tetsuya Katou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.
摘要翻译： ESD（静电放电）分析装置包括：电路模拟单元; 边界细胞提取单元; 和支票单位。电路模拟单元执行包括多个电源系统的多个电路的半导体集成电路的设计数据的电路仿真，以计算多个电源系统中不同的两个电源系统的焊盘之间的多个电流路径中的电位当ESD垫片之间施加ESD电流和ESD电压之一时。边界单元提取单元从多个电源系统中的不同两个电路的电路中提取边界单元，其中电路包括在多个电路中，边界单元在电路之间输入和/或输出信号。检查单元通过基于所计算的电位，提取的边界单元计算边界单元之间的电势差来检查ESD容限。

6. 发明授权

US07843008B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07843008B2
公开(公告)日：2010-11-30
申请号：US11727741
申请日：2007-03-28
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.
摘要翻译：能够快速高效地将已经产生在ESD保护元件中的散热的半导体器件快速高效地包括具有漏极区域，源极区域和栅极电极以及热扩散部分的ESD保护元件。已经形成在漏极区域上的热扩散部分具有与焊盘电连接的金属层，并且连接漏区和金属层的触点。金属层具有沿着栅电极延伸的第一布线，并且第二布线迹线垂直地与第一布线迹线相交。触点连接到第一布线和第二布线之间的交点。在ESD保护元件的pn结上产生并通过接触传递的热量通过金属层中的第一布线迹线和第二布线迹线在三个方向上同时扩散并被释放到焊盘中。

7. 发明授权

US08587908B2 Semiconductor device 有权
公开(公告)号：US08587908B2
公开(公告)日：2013-11-19
申请号：US13011622
申请日：2011-01-21
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H02H9/04
摘要： It is desired to effectively suppress breaking of a protection target circuit caused by direct application of an ESD surge voltage to the circuit. The semiconductor device includes: a VDD pad; a signal output pad; a GND pad; a high-potential power source line; a signal line; a low-potential power source line; main ESD protection elements; a PMOS transistor; and an output circuit. The output circuit includes: an NMOS transistor N1 whose source is connected to the signal line, and whose drain is connected to the low-potential power source line; and an NMOS transistor N2 connected between the gate of the NMOS transistor N1 and the low-potential power source line. The source of the PMOS transistor is connected to the signal line, the drain thereof is connected to the gate of the NMOS transistor N1, and the gate and back gate thereof are connected to the high-potential power source line.

8. 发明授权

US08283728B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08283728B2
公开(公告)日：2012-10-09
申请号：US12926708
申请日：2010-12-06
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H01L27/06 , H01L23/62
CPC分类号： H01L27/0266 , H01L24/06 , H01L2224/05554 , H01L2924/12036 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device includes a power supply line supplied with a power supply voltage; a power supply node connected with the power supply line; a ground line; a ground pad connected with the ground line; a signal input pad; a main protection circuit section configured to discharge an ESD surge applied to a first pad as one of the power supply node, the signal input pad and the ground pad to a second pad as another thereof; a protection object circuit; a connection node connected with the protection object circuit; a first resistance element connected between the signal input pad and the connection node; and a sub protection circuit section. The sub protection circuit section includes a least one of a first PMOS transistor having a source connected with the connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with the connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line.
摘要翻译：半导体器件包括供给电源电压的电源线; 与电源线连接的电源节点; 地线与接地线连接的接地垫; 信号输入板; 主保护电路部，被配置为将施加到作为所述电源节点之一的所述第一焊盘的ESD浪涌，所述信号输入焊盘和所述接地焊盘另一个放电到第二焊盘; 保护对象电路; 与保护对象电路连接的连接节点; 连接在信号输入板和连接节点之间的第一电阻元件; 和子保护电路部分。子保护电路部分包括具有与连接节点连接的源极的第一PMOS晶体管，与接地线连接的漏极和与电源线连接的栅极和后栅极中的至少一个，以及第一NMOS晶体管，其具有与连接节点连接的源极，与电源线连接的漏极以及与接地线连接的栅极和后栅极。

9. 发明授权

US08072720B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US08072720B2
公开(公告)日：2011-12-06
申请号：US12078977
申请日：2008-04-09
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K17/08104
摘要： An electrostatic protection circuit that affords protection without effecting transfer of an ordinary output signal includes an output terminal; a ground terminal; a first N-channel transistor having its drain and source connected between the output terminal and the ground terminal GND; a first electrostatic protection element connecting the output terminal and the ground terminal; and a second electrostatic protection element connected the drain and gate of the first N-channel transistor. The second N-channel transistor is connected to the gate of the first N-channel transistor. The gate potential of the first N-channel transistor rises and the gate-to-drain voltage of the first N-channel transistor is limited to a value below a prescribed value by a current that flows into the second electrostatic protection element owing to application of static electricity to the output terminal, and resistance of the second N-channel transistor, which is the ON state, as seen from the gate of the first N-channel transistor.
摘要翻译：提供保护而不影响普通输出信号的传输的静电保护电路包括输出端子; 地面终端; 第一N沟道晶体管，其漏极和源极连接在输出端和接地端GND之间; 连接输出端子和接地端子的第一静电保护元件; 以及连接第一N沟道晶体管的漏极和栅极的第二静电保护元件。第二N沟道晶体管连接到第一N沟道晶体管的栅极。第一N沟道晶体管的栅极电位上升，第一N沟道晶体管的栅极至漏极电压由于施加到第二静电保护元件的电流而被限制在低于规定值的值从第一N沟道晶体管的栅极看到的是输出端子的静电和作为导通状态的第二N沟道晶体管的电阻。

10. 发明申请

US20110133282A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20110133282A1
公开(公告)日：2011-06-09
申请号：US12926708
申请日：2010-12-06
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H01L27/06
CPC分类号： H01L27/0266 , H01L24/06 , H01L2224/05554 , H01L2924/12036 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device includes a power supply line supplied with a power supply voltage; a power supply node connected with the power supply line; a ground line; a ground pad connected with the ground line; a signal input pad; a main protection circuit section configured to discharge an ESD surge applied to a first pad as one of the power supply node, the signal input pad and the ground pad to a second pad as another thereof; a protection object circuit; a connection node connected with the protection object circuit; a first resistance element connected between the signal input pad and the connection node; and a sub protection circuit section. The sub protection circuit section includes a least one of a first PMOS transistor having a source connected with the connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with the connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line.
摘要翻译：半导体器件包括供给电源电压的电源线; 与电源线连接的电源节点; 地线与接地线连接的接地垫; 信号输入板; 主保护电路部，被配置为将施加到作为所述电源节点之一的所述第一焊盘的ESD浪涌，所述信号输入焊盘和所述接地焊盘另一个放电到第二焊盘; 保护对象电路; 与保护对象电路连接的连接节点; 连接在信号输入板和连接节点之间的第一电阻元件; 和子保护电路部分。子保护电路部分包括具有与连接节点连接的源极的第一PMOS晶体管，与接地线连接的漏极和与电源线连接的栅极和后栅极中的至少一个，以及第一NMOS晶体管，其具有与连接节点连接的源极，与电源线连接的漏极以及与接地线连接的栅极和后栅极。

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