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1. 发明申请

US20110022934A1 SYSTEM AND APPARATUS FOR SYNCHRONIZATION BETWEEN HETEROGENEOUS PERIODIC CLOCK DOMAINS, CIRCUIT FOR DETECTING SYNCHRONIZATION FAILURE AND DATA RECEIVING METHOD 有权
标题翻译：用于同步异步时钟域之间的同步的系统和装置，用于检测同步故障的电路和数据接收方法
公开(公告)号：US20110022934A1
公开(公告)日：2011-01-27
申请号：US12825919
申请日：2010-06-29
申请人： Myeong Hoon OH , Seong Woon KIM
发明人： Myeong Hoon OH , Seong Woon KIM
IPC分类号： G06F11/07
CPC分类号： H04L7/0008 , G06F1/10 , G06F1/12
摘要： The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock.
摘要翻译：本发明涉及异构周期性时钟域之间的同步系统和装置，同步故障检测电路和数据接收方法。包括发送器和接收器的异步周期性时钟域之间的同步系统分别根据异构的周期性第一时钟和第二时钟操作，包括：发送器，其输出通过第一时间延迟第一时钟获得的预测时钟; 以及接收器，其通过使用所述预测时钟来预测所述第一时钟和所述第二时钟之间的同步的成功和失败，并且根据所述预测结果选择性地延迟所述第二时钟，以使所述第二时钟与所述第一时钟同步。

2. 发明申请

US20120102300A1 ASYNCHRONOUS PIPELINE SYSTEM, STAGE, AND DATA TRANSFER MECHANISM 有权
标题翻译：非同步管道系统，阶段和数据传输机制
公开(公告)号：US20120102300A1
公开(公告)日：2012-04-26
申请号：US13278385
申请日：2011-10-21
申请人： Myeong Hoon OH , Young Woo KIM , Sung Nam KIM , Seong Woon KIM
发明人： Myeong Hoon OH , Young Woo KIM , Sung Nam KIM , Seong Woon KIM
IPC分类号： G06F15/00 , G06F9/315
CPC分类号： G06F9/3871 , G06F9/3869
摘要： Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.
摘要翻译：公开了异步管线系统，阶段和数据传输机制。具有基于四相协议的多级的异步管线系统包括：多级中的第一级; 以及与第一级相邻的多级中的第二级，其中第一级发送，第二级通过始终捆绑的数据信道和按需数据信道通过按需数据信道来接收捆绑数据和控制数据，根据需要第二阶段

3. 发明申请

US20080133798A1 PACKET RECEIVING HARDWARE APPARATUS FOR TCP OFFLOAD ENGINE AND RECEIVING SYSTEM AND METHOD USING THE SAME 失效
标题翻译：用于TCP卸载发动机和接收系统的分组接收硬件设备及其使用方法
公开(公告)号：US20080133798A1
公开(公告)日：2008-06-05
申请号：US11949738
申请日：2007-12-03
申请人： Chan Ho PARK , Seong Woon KIM , Myung Joon KIM
发明人： Chan Ho PARK , Seong Woon KIM , Myung Joon KIM
IPC分类号： G06F5/14
CPC分类号： H04L69/16 , H04L47/193 , H04L47/2441 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/161 , H04L69/163 , H04L69/22
摘要： A hardware apparatus for receiving a packet for a TCP offload engine (TOE), and receiving system and method using the same are provided. Specifically, information required to protocol processing by a processor is stored in the internal queue included in the packet receiving hardware. Data to be stored in a host memory is transmitted to the host memory after the data is stored in an external memory and protocol processing is performed by the processor. With these techniques, it is possible that a processor can operate asynchronously with a receiving time of a practical packet and it is possible to reduce an overhead that processor deals with unnecessary information
摘要翻译：提供了一种用于接收用于TCP卸载引擎（TOE）的分组的硬件装置，以及使用其的接收系统和方法。具体地，由处理器进行协议处理所需的信息被存储在分组接收硬件中包括的内部队列中。在将数据存储在外部存储器中并且由处理器执行协议处理之后，要存储在主机存储器中的数据被发送到主机存储器。利用这些技术，处理器可能与实际分组的接收时间异步地操作，并且可以减少处理器处理不必要的信息的开销

4. 发明申请

US20110131646A1 APPARATUS AND METHOD FOR PREVENTING NETWORK ATTACKS, AND PACKET TRANSMISSION AND RECEPTION PROCESSING APPARATUS AND METHOD USING THE SAME 审中-公开
标题翻译：用于防止网络攻击的装置和方法，以及分组传输和接收处理装置及其使用方法
公开(公告)号：US20110131646A1
公开(公告)日：2011-06-02
申请号：US12701253
申请日：2010-02-05
申请人： Chanho PARK , Seong Woon KIM , Sun Wook KIM
发明人： Chanho PARK , Seong Woon KIM , Sun Wook KIM
IPC分类号： G06F17/00
CPC分类号： H04L63/1458 , H04L63/0236 , H04L63/0254
摘要： An apparatus for preventing network attacks includes: a packet buffer for storing received packets from a network; a filtering unit for filtering harmful packets based on a result of comparison between information of the received packets and preset filtering information to select a first filtering target packet; an SYN cookie handler for selecting a second filtering target packet using an SYN cookie if it is determined that there is a TCP SYN flooding attack based on the information of the received packets after said filtering; and a session manager for selecting a third filtering target packet through session management if there is a TCP flag flooding attack based on the information of the received packets after said filtering. The apparatus further includes a packet transmission and receipt processing method and apparatus using above.
摘要翻译：一种用于防止网络攻击的装置包括：分组缓冲器，用于存储来自网络的接收到的分组; 基于所接收的分组的信息与预设的过滤信息的比较结果对有害分组进行过滤的过滤单元，以选择第一过滤目标分组; 如果在所述过滤之后确定基于所接收的分组的信息确定存在TCP SYN洪泛攻击，则使用SYN cookie来选择第二过滤目标分组的SYN cookie处理器; 以及会话管理器，用于在所述过滤之后基于所接收的分组的信息，如果存在TCP标志洪泛攻击，则通过会话管理来选择第三过滤目标分组。该装置还包括上述使用的分组发送和接收处理方法和装置。

5. 发明申请

US20140195742A1 SYSTEM ON CHIP INCLUDING MEMORY MANAGEMENT UNIT AND MEMORY ADDRESS TRANSLATION METHOD THEREOF 有权
标题翻译：芯片系统，包括存储器管理单元和存储器地址转换方法
公开(公告)号：US20140195742A1
公开(公告)日：2014-07-10
申请号：US14138982
申请日：2013-12-23
申请人： Seok Min KIM , Kwan Ho KIM , Seong Woon KIM , Tae Sun KIM , Kyoung Mook LIM
发明人： Seok Min KIM , Kwan Ho KIM , Seong Woon KIM , Tae Sun KIM , Kyoung Mook LIM
IPC分类号： G06F12/10 , G06F12/02 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0813 , G06F12/1072 , G06F2212/306
摘要： A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.
摘要翻译：提供了包括存储器管理单元（MMU）及其存储器地址转换方法的片上系统（SoC）。所述SoC包括配置为输出与多个工作组中的每一个对应的请求的主知识产权（IP）; 一个MMU模块，包括多个MMU，每个MMU被分配用于一个工作组，并将与该请求对应的虚拟地址转换成物理地址; 第一总线互连配置为将MMU模块与存储器装置连接并且将已经在至少一个MMU中进行了地址转换的请求发送到存储器装置; 以及第二总线互连，其被配置为将主IP与MMU模块连接，并为每个工作集分配一个MMU。

6. 发明申请

US20110116795A1 OPTICAL I/O BUS SYSTEM 有权
标题翻译：光学I / O总线系统
公开(公告)号：US20110116795A1
公开(公告)日：2011-05-19
申请号：US12705220
申请日：2010-02-12
申请人： Hyo Hoon PARK , Tae Woo LEE , Mu Hee CHO , Seong Woon KIM , Min Hyuk LEE
发明人： Hyo Hoon PARK , Tae Woo LEE , Mu Hee CHO , Seong Woon KIM , Min Hyuk LEE
IPC分类号： H04B10/20 , H04J14/00
CPC分类号： G02B6/43 , H04B10/801
摘要： An optical input/output (I/O) bus system for connecting a plurality of external devices with a central processing unit (CPU) or memory in a specific system using an optical signal is provided. The optical I/O bus system includes a serializer and deserializer (SerDes) connected with the CPU or memory, and configured to divide a serial electrical signal into parallel electrical signals or combine parallel electrical signals into a serial electrical signal, a photoelectric converter prepared between the SerDes and the external devices, and configured to convert the serial/parallel electrical signals into an optical signal or an optical signal into an electrical signal, a plurality of optical transmission means disposed in parallel to transfer the optical signal converted by the photoelectric converter, an optical switch prepared between the photoelectric converter and the optical transmission means, and configured to switch to one of the optical transmission means to transfer the optical signal converted by the photoelectric converter to the optical transmission means according to an address of the optical signal, and a plurality of optical slots connected to the respective optical transmission means to connect the external devices so that the optical signal is input/output. In the optical I/O bus system, a high-capacity signal can be transferred without distortion, interference, and bottleneck using optical connection technology.
摘要翻译：提供了一种用于使用光信号将多个外部设备与特定系统中的中央处理单元（CPU）或存储器连接的光输入/输出（I / O）总线系统。光学I / O总线系统包括与CPU或存储器连接的串行器和解串器（SerDes），并被配置为将串行电信号划分为并行电信号或将并行电信号组合成串行电信号，光电转换器 SerDes和外部设备，并且被配置为将串行/并行电信号转换为光信号或光信号为电信号;并行设置的多个光传输装置，用于传送由光电转换器转换的光信号，在所述光电转换器和所述光传输装置之间准备的光开关，并且被配置为切换到所述光传输装置之一以根据所述光信号的地址将由所述光电转换器转换的光信号传送到所述光传输装置，以及多个光插槽连接到相应的选择连接外部设备，使光信号输入/输出。在光I / O总线系统中，使用光连接技术可以传输大容量信号而无失真，干扰和瓶颈。

7. 发明申请

US20100042860A1 RACK POWER SUPPLY SYSTEM AND METHOD OF CONTROLLING RACK POWER SUPPLY APPARATUS 审中-公开
标题翻译：机架电源系统和控制机架电源设备的方法
公开(公告)号：US20100042860A1
公开(公告)日：2010-02-18
申请号：US12414072
申请日：2009-03-30
申请人： Won Ok KWON , Seong Woon KIM , Myung Joon KIM
发明人： Won Ok KWON , Seong Woon KIM , Myung Joon KIM
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： Provided is a method of controlling a rack power supply system and a rack power supply apparatus. The system includes a plurality of computing devices mounted in a rack, and a rack power supply apparatus supplying the plurality of computing devices with direct current (DC) power. The rack power supply apparatus includes a plurality of power generating units and a control unit. The plurality of power generating units are supplied with alternating current (AC) power to generate the DC power. The control unit controls to turn on or off each power generating unit in consideration of power consumption.
摘要翻译：提供了一种控制机架电源系统和机架电源装置的方法。该系统包括安装在机架中的多个计算装置和向多个计算装置提供直流（DC）功率的机架电源装置。机架供电装置包括多个发电单元和控制单元。多个发电单元被提供有交流（AC）电力以产生直流电力。考虑到功率消耗，控制单元控制打开或关闭每个发电单元。

8. 发明申请

US20110116807A1 EXPRESS INTERFACE APPARATUS USING OPTICAL CONNECTION 审中-公开
标题翻译：使用光学连接的EXPRESS接口设备
公开(公告)号：US20110116807A1
公开(公告)日：2011-05-19
申请号：US12696668
申请日：2010-01-29
申请人： Hyo Hoon PARK , Tae Woo LEE , Min Hyuk LEE , Mu Hee CHO , Seong Woon KIM
发明人： Hyo Hoon PARK , Tae Woo LEE , Min Hyuk LEE , Mu Hee CHO , Seong Woon KIM
IPC分类号： H04B10/00
CPC分类号： H04B10/801
摘要： An express interface apparatus using an optical connection is provided. The apparatus connects between a central processing unit (CPU) in a computer system and an external device supporting optical signal transfer using a peripheral component interconnect express (PCIE) supporting high-speed signal processing. The apparatus includes an optical connection module for connecting the external device so that an optical signal is input/output; an optical-to-electrical conversion module for converting the optical signal from the optical connection module into an electrical signal or converting an electrical signal into an optical signal; a signal processing module connected to the optical-to-electrical conversion module for performing signal processing to divide or merge the electrical signal; and a PCIE control module for controlling a processed signal from the signal processing module to deliver the signal to the CPU via a PCIE slot and controlling high-speed data transmitted and received between the CPU and the external device, such that a signal can be transmitted and received without a distortion or bottleneck phenomenon in high-speed data transfer.
摘要翻译：提供了一种使用光学连接的快速接口装置。该装置连接在计算机系统中的中央处理单元（CPU）和支持光信号传输的外部设备之间，该外部设备使用支持高速信号处理的外围组件互连快速（PCIE）。该装置包括用于连接外部设备以使光信号被输入/输出的光学连接模块; 光电转换模块，用于将来自光连接模块的光信号转换为电信号或将电信号转换为光信号; 连接到光电转换模块的信号处理模块，用于执行信号处理以分割或合并电信号; 以及PCIE控制模块，用于控制来自信号处理模块的经处理的信号，以经由PCIE插槽向CPU发送信号，并控制在CPU和外部设备之间发送和接收的高速数据，使得可以发送信号并在高速数据传输中没有发生失真或瓶颈现象。

9. 发明申请

US20110006607A1 HYBRID POWER SUPPLY APPARATUS FOR DATA CENTER 审中-公开
标题翻译：用于数据中心的混合电源设备
公开(公告)号：US20110006607A1
公开(公告)日：2011-01-13
申请号：US12638426
申请日：2009-12-15
申请人： Won-Ok KWON , Seong Woon KIM
发明人： Won-Ok KWON , Seong Woon KIM
IPC分类号： H02J9/00
CPC分类号： H02J1/102 , G06F1/30 , H02J9/062 , H02J2001/008 , Y10T307/625
摘要： A hybrid power supply apparatus for data center includes: one or more power sources; and an uninterruptible rack level power supply unit supplied with an Alternating Current (AC) power from said one or more power sources, and configured to supply Direct Current (DC) power to a rack, the power supply unit supplying the DC power to the rack without interruption when supply of the power from said one or more power sources is stopped. The apparatus further includes a node provided in the rack and supplied with the DC power from the uninterruptible rack level power supply unit.
摘要翻译：一种用于数据中心的混合供电装置包括：一个或多个电源; 以及不间断的机架级电源单元，其被提供有来自所述一个或多个电源的交流电（AC）电力，并被配置为向机架提供直流（DC）电力，所述电源单元向所述机架提供直流电力当来自所述一个或多个电源的电力供应停止时，不中断。该装置还包括设置在机架中并且提供来自不间断机架级电源单元的直流电力的节点。

10. 发明申请

US20080140687A1 SOCKET STRUCTURE SIMULTANEOUSLY SUPPORTING BOTH TOE AND ETHERNET NETWORK INTERFACE CARD AND METHOD OF FORMING THE SOCKET STRUCTURE 审中-公开
标题翻译：插座结构同时支持两个托盘和以太网网络接口卡和形成插座结构的方法
公开(公告)号：US20080140687A1
公开(公告)日：2008-06-12
申请号：US11875021
申请日：2007-10-19
申请人： Soo Cheol OH , Seong Woon KIM
发明人： Soo Cheol OH , Seong Woon KIM
IPC分类号： G06F17/30
CPC分类号： H04L69/16 , H04L49/90 , H04L69/12 , H04L69/161 , H04L69/162 , H04L69/168
摘要： A socket structure simultaneously supporting a Transmission Control Protocol/Internet Protocol (TCP/IP) offload engine and an Ethernet network interface card (NIC), the socket structure including: an NIC management module storing and managing pointer information with respect to a socket structure for supporting a Berkeley software distribution (BSD) socket interface; and a TCP/IP offload engine (TOE) management module storing and managing identification information with respect to a socket directly managed by TOE hardware.
摘要翻译：一种同时支持传输控制协议/互联网协议（TCP / IP）卸载引擎和以太网网络接口卡（NIC）的套接字结构，该套接字结构包括：NIC管理模块，用于存储和管理关于插座结构的指针信息，支持Berkeley软件分发（BSD）套接字接口; 以及TCP / IP卸载引擎（TOE）管理模块，用于存储和管理由TOE硬件直接管理的套接字的识别信息。

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