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1. 发明授权

US11621723B2 Input-shaping method and input-shaping unit for group-modulated input scheme in computing-in-memory applications 有权
公开(公告)号：US11621723B2
公开(公告)日：2023-04-04
申请号：US17200927
申请日：2021-03-15
申请人： NATIONAL TSING HUA UNIVERSITY
发明人： Fu-Chun Chang , Ta-Wei Liu , Cheng-Xin Xue , Sheng-Po Huang , Yen-Hsiang Huang , Meng-Fan Chang
IPC分类号： H03M7/30 , G06N5/04 , G06F21/32 , G06N3/063 , G06F9/50 , G06N3/04 , G06F9/46
摘要： An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.

2. 发明授权

US09502114B1 Non-volatile ternary content-addressable memory with bi-directional voltage divider control and multi-step search 有权
标题翻译：非易失性三元内容可寻址存储器，具有双向分压器控制和多步搜索
公开(公告)号：US09502114B1
公开(公告)日：2016-11-22
申请号：US14941587
申请日：2015-11-14
申请人： National Tsing Hua university
发明人： Chien-Chen Lin , Albert Lee , Chieh-Pu Lo , Meng-Fan Chang
IPC分类号： G11C15/04 , G11C15/02
CPC分类号： G11C15/046 , G11C15/02
摘要： A cell for a non-volatile ternary content-addressable (TCAM) memory is provided. The cell comprises a first variable resistive element, a first transistor and a charge control transistor. Two terminals of the first variable resistive element are respectively electrically coupled to a first search-line and a storage node. A drain electrode of the first transistor is electrically coupled to the storage node. A source electrode of the first transistor is electrically coupled to a low-side search-line. A gate electrode of the charge control transistor coupled to a match-line is electrically coupled to the storage node. When the cell operates in a search phase and the first transistor is turned on, a pulse voltage is applied across the first search-line and the low-side search-line for determining whether the voltage of the storage node is larger than a match threshold during the period of the pulse.
摘要翻译：提供了一种用于非易失性三元内容可寻址（TCAM）存储器的单元。该单元包括第一可变电阻元件，第一晶体管和电荷控制晶体管。第一可变电阻元件的两个端子分别电耦合到第一搜索线和存储节点。第一晶体管的漏极电连接到存储节点。第一晶体管的源电极电耦合到低边搜索线。耦合到匹配线的电荷控制晶体管的栅电极电耦合到存储节点。当单元在搜索阶段中操作并且第一晶体管导通时，跨越第一搜索线和低边搜索线施加脉冲电压，以确定存储节点的电压是否大于匹配阈值在脉搏期间。

3. 发明授权

US09431070B1 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US09431070B1
公开(公告)日：2016-08-30
申请号：US14840054
申请日：2015-08-31
申请人： National Tsing Hua University
发明人： Meng-Fan Chang , Yu-Lin Chen , Chia-Yin Li , Tien-Fu Chen , Keng-Hao Yang
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C11/16 , G11C13/00 , G11C11/419 , G11C7/12
CPC分类号： G11C7/062 , G11C7/12 , G11C11/1673 , G11C11/4091 , G11C11/419 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C15/02 , G11C15/04 , G11C15/043 , G11C15/046
摘要： The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.
摘要翻译：本公开提供一种存储装置，包括存储单元阵列，多个读出放大器，至少一个第一比较电路和多个第二比较电路。存储单元阵列包括多个存储单元。每个读出放大器根据位线信号和反相位线信号产生数据信号和反相数据信号。第一比较电路将第一和第二读出放大器的数据信号与第一标签进行比较，以产生第一比较结果。第二比较电路分别将多个第二标签与读出放大器的数据信号进行比较，以分别产生多个第二比较结果。

4. 发明授权

US11057224B1 Method and system for performing physical unclonable function generated by non-volatile memory write delay difference 有权
公开(公告)号：US11057224B1
公开(公告)日：2021-07-06
申请号：US16729512
申请日：2019-12-30
申请人： NATIONAL TSING HUA UNIVERSITY
发明人： Meng-Fan Chang
IPC分类号： G11C11/34 , H04L9/32 , G11C16/10
摘要： A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.

5. 发明授权

US11049550B1 Multi-bit current sense amplifier with pipeline current sampling of resistive memory array structure and sensing method thereof 有权
公开(公告)号：US11049550B1
公开(公告)日：2021-06-29
申请号：US16904577
申请日：2020-06-18
申请人： NATIONAL TSING HUA UNIVERSITY
发明人： Tung-Cheng Chang , Chun-Ying Lee , Meng-Fan Chang
IPC分类号： G11C13/02 , G11C7/06 , G11C7/02 , G11C11/4091 , G11C11/4094 , G11C5/02 , G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C13/00 , G11C16/26 , G11C7/12 , G11C11/16 , G11C11/56
摘要： A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.

6. 发明授权

US10510386B1 Dynamic bit-line clamping circuit for computing-in-memory applications and clamping method thereof 有权
公开(公告)号：US10510386B1
公开(公告)日：2019-12-17
申请号：US16115582
申请日：2018-08-29
申请人： NATIONAL TSING HUA UNIVERSITY
发明人： Meng-Fan Chang , Wei-Hao Chen , Wei-Yu Lin
IPC分类号： G11C7/12 , G11C7/06
摘要： A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.

7. 发明授权

US10249360B1 Method and circuit for generating a reference voltage in neuromorphic system 有权
公开(公告)号：US10249360B1
公开(公告)日：2019-04-02
申请号：US15827737
申请日：2017-11-30
申请人： National Tsing Hua University
发明人： Meng-Fan Chang , Win-San Khwa , Jia-Jing Chen
IPC分类号： G11C11/4099 , G06N3/063 , G06N3/10 , G11C13/00 , G11C11/419 , G11C11/54 , G06N3/04
摘要： A method and a circuit for generating a reference voltage are provided. The circuit includes: a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1, wherein the plurality word-lines are connected to the dummy neurons in the first and second columns, respectively; a bit-line connected to a voltage source and the first column of dummy neurons; a complementary bit-line is connected to the voltage source and the second column of dummy neurons, wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.

8. 发明授权

US09722584B1 Non-volatile latch 有权
公开(公告)号：US09722584B1
公开(公告)日：2017-08-01
申请号：US15134046
申请日：2016-04-20
申请人： National Tsing Hua University
发明人： Meng-Fan Chang , Albert Lee , Chieh-Pu Lo , Chien-Chen Lin
IPC分类号： G11C7/10 , H03K3/356 , H03K3/037 , G11C13/00
CPC分类号： H03K3/356008 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C14/009 , G11C2013/0066 , G11C2013/009 , H03K3/0375
摘要： Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.

9. 发明授权

US09484096B1 Ternary content-addressable memory 有权
标题翻译：三进制内容可寻址内存
公开(公告)号：US09484096B1
公开(公告)日：2016-11-01
申请号：US14954935
申请日：2015-11-30
申请人： NATIONAL TSING HUA UNIVERSITY
发明人： Chien-Fu Chen , Chien-Chen Lin , Meng-Fan Chang
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/043 , G11C15/046
摘要： A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access memory cell. The first switch is connected between a first search line and a match line. The first switch has a first control electrode. The first static random-access memory cell has a first storage node connected to the first control electrode of the first switch. The second switch is connected between a second search line and the match line. The second switch has a second control node. The second static random-access memory cell has a second storage node connected to the second control electrode of the second switch.
摘要翻译：三进制内容可寻址存储器包括第一开关，第一静态随机存取存储器单元，第二开关和第二静态随机存取存储器单元。第一开关连接在第一搜索线和匹配线之间。第一开关具有第一控制电极。第一静态随机存取存储单元具有连接到第一开关的第一控制电极的第一存储节点。第二开关连接在第二搜索线和匹配线之间。第二开关具有第二控制节点。第二静态随机存取存储单元具有连接到第二开关的第二控制电极的第二存储节点。

10. 发明授权

US09312006B2 Non-volatile ternary content-addressable memory with resistive memory device 有权
标题翻译：具有电阻式存储器件的非易失性三元内容可寻址存储器
公开(公告)号：US09312006B2
公开(公告)日：2016-04-12
申请号：US14294174
申请日：2014-06-03
申请人： National Tsing Hua University
发明人： Meng-Fan Chang , Ching-Hao Chuang
IPC分类号： G11C15/00 , G11C15/04 , G11C5/06 , G11C13/00
CPC分类号： G11C15/046 , G11C5/06 , G11C13/0002
摘要： A scheme for non-volatile ternary content-addressable memory with resistive memory device is proposed. The non-volatile ternary content-addressable memory comprises five transistors including a pair of search transistors with a first search transistor and a second search transistor, a read transistor, a write transistor and a match line transistor, wherein a match line is coupled to the match line transistor; and a pair of variable resistances have a first variable resistance and a second variable resistance. The pair of search transistors is coupled to the pair of variable resistances.
摘要翻译：提出了一种具有电阻式存储器件的非易失性三元内容可寻址存储器的方案。非挥发性三元内容可寻址存储器包括五个晶体管，包括具有第一搜索晶体管和第二搜索晶体管的一对搜索晶体管，读取晶体管，写入晶体管和匹配线晶体管，其中匹配线耦合到匹配线晶体管; 并且一对可变电阻具有第一可变电阻和第二可变电阻。该对搜索晶体管耦合到该对可变电阻。

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