专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09823931B2 Queued instruction re-dispatch after runahead 有权
公开(公告)号：US09823931B2
公开(公告)日：2017-11-21
申请号：US13730407
申请日：2012-12-28
申请人： NVIDIA Corporation
发明人： Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman , Aravindh Baktha , David Dunn
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/3842 , G06F9/3863
摘要： Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

2. 发明申请

US20140189313A1 QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD 有权
标题翻译：在RUNAHEAD之后的QUEUED指令重新分配
公开(公告)号：US20140189313A1
公开(公告)日：2014-07-03
申请号：US13730407
申请日：2012-12-28
申请人： NVIDIA CORPORATION
发明人： Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman , Aravindh Baktha , David Dunn
IPC分类号： G06F9/30
CPC分类号： G06F9/3814 , G06F9/3842 , G06F9/3863
摘要： Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.
摘要翻译：这里公开了微流器的各种实施例以及在径流操作期间操作微处理器的方法。操作微处理器的一个示例性方法包括识别与跑步头触发指令相关联的跑跑前触发事件，并且响应于跑步头触发事件的识别，进入跑步头操作并将一个或多个附加指令连同插入跑步头触发指令在队列中示例性方法还包括响应于前导触发事件的解决恢复微处理器的非跑跑操作，以及将一个或多个附加指令与队列中的一个或多个附加指令重新分派到执行逻辑。

3. 发明申请

US20140164738A1 INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION 审中-公开
标题翻译： RUNAHEAD操作的指令分类
公开(公告)号：US20140164738A1
公开(公告)日：2014-06-12
申请号：US13708544
申请日：2012-12-07
申请人： NVIDIA CORPORATION
发明人： Magnus Ekman , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/3842 , G06F9/3861
摘要： Embodiments related to methods and devices operative, in the event that execution of an instruction produces a runahead-triggering event, to cause a microprocessor to enter into and operate in a runahead without reissuing the instruction are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic for retrieving an instruction, scheduling logic for issuing the instruction retrieved by the fetch logic for execution, and runahead control logic. The example runahead control logic is operative, in the event that execution of the instruction as scheduled by the scheduling logic produces a runahead-triggering event, to cause the microprocessor to enter into and operate in a runahead mode without reissuing the instruction, and carry out runahead policies while the microprocessor is in the runahead mode that governs operation of the microprocessor and cause the microprocessor to operate differently than when not in the runahead mode.
摘要翻译：提供了与方法和设备相关的实施例，其中在指令的执行产生跑道前触发事件的情况下，提供微处理器进入并在没有重新发出指令的情况下操作。在一个示例中，提供微处理器。示例微处理器包括用于检索指令的提取逻辑，用于发出由执行提取逻辑检索的指令的调度逻辑以及前导控制逻辑。示例性跑步头控制逻辑是可操作的，在由调度逻辑调度的指令的执行产生跑道前触发事件的情况下，使得微处理器进入并运行在跑步模式中而不重新发出指令，并执行微处理器处于控制微处理器操作的跑头模式，并导致微处理器的操作与不在跑头模式时的运行不同。

4. 发明申请

US20170199778A1 LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR 审中-公开
公开(公告)号：US20170199778A1
公开(公告)日：2017-07-13
申请号：US15470602
申请日：2017-03-27
申请人： NVIDIA CORPORATION
发明人： Magnus Ekman , Ross Segelken , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Darrell D. Boggs
IPC分类号： G06F11/07 , G06F9/30 , G06F9/38 , G06F15/78
CPC分类号： G06F11/0721 , G06F9/30087 , G06F9/30181 , G06F9/3842 , G06F9/3851 , G06F11/0793 , G06F15/78
摘要： Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

5. 发明申请

US20140136891A1 MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD 有权
标题翻译：在RUNAHEAD期间管理潜在的无效结果
公开(公告)号：US20140136891A1
公开(公告)日：2014-05-15
申请号：US13677085
申请日：2012-11-14
申请人： NVIDIA CORPORATION
发明人： Bruce Holmer , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3865 , G06F11/004 , G06F11/0721 , G06F11/0763
摘要： Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
摘要翻译：提供了与在管理头期间由微处理器生成/获得的潜在无效结果相关的实施例。在一个示例中，用于操作微处理器的方法包括使微处理器在检测到跑道事件时进入跑道头。示例性方法还包括在跑步头期间，确定与基于存储位置的指令相关联的操作将基于与存储位置相关联的架构毒性比特的值产生潜在的无效结果，并且响应于不同的操作。

6. 发明授权

US09740553B2 Managing potentially invalid results during runahead 有权
公开(公告)号：US09740553B2
公开(公告)日：2017-08-22
申请号：US13677085
申请日：2012-11-14
申请人： NVIDIA Corporation
发明人： Bruce Holmer , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman
IPC分类号： G06F15/00 , G06F7/38 , G06F11/07 , G06F11/00 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3865 , G06F11/004 , G06F11/0721 , G06F11/0763
摘要： Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

7. 发明授权

US09632976B2 Lazy runahead operation for a microprocessor 有权
公开(公告)号：US09632976B2
公开(公告)日：2017-04-25
申请号：US13708645
申请日：2012-12-07
申请人： NVIDIA Corporation
发明人： Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman
IPC分类号： G06F11/00 , G06F15/78 , G06F9/30 , G06F9/38 , G06F11/07
CPC分类号： G06F11/0721 , G06F9/30087 , G06F9/30181 , G06F9/3842 , G06F9/3851 , G06F11/0793 , G06F15/78
摘要： Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

8. 发明申请

US20140281259A1 TRANSLATION LOOKASIDE BUFFER ENTRY SYSTEMS AND METHODS 有权
标题翻译：翻译LOOKASIDE缓冲进入系统和方法
公开(公告)号：US20140281259A1
公开(公告)日：2014-09-18
申请号：US13831176
申请日：2013-03-14
申请人： NVIDIA CORPORATION
发明人： Alexander Klaiber , William Rozas
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0862 , G06F12/1027
摘要： Presented systems and methods can facilitate efficient information storage and tracking operations, including translation look aside buffer operations. In one embodiment, the systems and methods effectively allow the caching of invalid entries (with the attendant benefits e.g., regarding power, resource usage, stalls, etc), while maintaining the illusion that the TLBs do not in fact cache invalid entries (e.g., act in compliance with architectural rules). In one exemplary implementation, an “unreal” TLB entry effectively serves as a hint that the linear address in question currently has no valid mapping. In one exemplary implementation, speculative operations that hit an unreal entry are discarded; architectural operations that hit an unreal entry discard the entry and perform a normal page walk, either obtaining a valid entry, or raising an architectural fault.
摘要翻译：提出的系统和方法可以促进有效的信息存储和跟踪操作，包括翻译旁边的缓冲操作。在一个实施例中，系统和方法有效地允许无效条目的缓存（伴随的优点，例如关于功率，资源使用，停顿等），同时保持TLB实际上不高速缓存无效条目的错觉（例如，按照建筑规则行事）。在一个示例性实现中，“虚幻”TLB条目有效地用作当前所讨论的线性地址没有有效映射的提示。在一个示例性实施方式中，命中不真实条目的推测操作被丢弃; 命中虚幻条目的架构操作会丢弃该条目并执行正常的页面散步，获取有效的条目或提升架构故障。

9. 发明授权

US10108424B2 Profiling code portions to generate translations 有权
公开(公告)号：US10108424B2
公开(公告)日：2018-10-23
申请号：US13828865
申请日：2013-03-14
申请人： NVIDIA Corporation
发明人： Nathan Tuck , Alexander Klaiber , Ross Segelken , David Dunn , Ben Hertzberg , Rupert Brauch , Thomas Kistler , Guillermo J. Rozas , Madhu Swarna
IPC分类号： G06F9/30 , G06F9/38 , G06F11/34
摘要： The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

10. 发明授权

US09891972B2 Lazy runahead operation for a microprocessor 有权
公开(公告)号：US09891972B2
公开(公告)日：2018-02-13
申请号：US15470602
申请日：2017-03-27
申请人： NVIDIA CORPORATION
发明人： Magnus Ekman , Ross Segelken , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Darrell D. Boggs
IPC分类号： G06F9/00 , G06F11/07 , G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F11/0721 , G06F9/30087 , G06F9/30181 , G06F9/3842 , G06F9/3851 , G06F11/0793 , G06F15/78
摘要： Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式