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1. 发明申请

US20150295051A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150295051A1
公开(公告)日：2015-10-15
申请号：US14668154
申请日：2015-03-25
申请人： NXP B.V.
发明人： Johannes Josephus Theodorus Marinus Donkers , Hans Broekman
IPC分类号： H01L29/20 , H01L29/778 , H01L29/66 , H01L29/205
CPC分类号： H01L29/2003 , H01L29/205 , H01L29/42316 , H01L29/452 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7786
摘要： A semiconductor device (100, 100′, 100″) and a method for manufacturing a semiconductor device (100, 100′, 100″). The semiconductor device (100, 100′, 100″) includes a substrate (104, 106), a GaN layer (112), and an AlGaN layer (114). The GaN layer (112) is located between the substrate (104, 106) and the AlGaN layer (114). The device further includes at least one contact (130, 132, 134), comprising a central portion (150) and an edge portion (152), and a passivation layer (160) located at least between the edge portion (152) of the contact (130, 132, 134) and the AlGaN layer (114). The edge portion (152) is spaced apart from an upper surface of the passivation layer (160). The edge portion (152) may be spaced apart from the passivation layer (160) by a further layer (170) or by an air gap (172).
摘要翻译：半导体器件（100,100'，100“）和半导体器件（100,100'，100”）的制造方法。半导体器件（100,100'，100“）包括衬底（104,106），GaN层（112）和AlGaN层（114）。 GaN层（112）位于衬底（104,106）和AlGaN层（114）之间。所述装置还包括至少一个包括中心部分（150）和边缘部分（152）的触点（130,132,134），以及至少位于所述边缘部分（152）的边缘部分（152）之间的钝化层接触（130,132,134）和AlGaN层（114）。边缘部分（152）与钝化层（160）的上表面间隔开。边缘部分（152）可以通过另外的层（170）或气隙（172）与钝化层（160）间隔开。

2. 发明授权

US08962461B2 GaN HEMTs and GaN diodes 有权
标题翻译： GaN HEMT和GaN二极管
公开(公告)号：US08962461B2
公开(公告)日：2015-02-24
申请号：US14108042
申请日：2013-12-16
申请人： NXP B.V.
发明人： Godefridus Adrianus Maria Hurkx , Jeroen Antoon Croon , Johannes Josephus Theodorus Marinus Donkers , Stephan Heil , Jan Sonsky
IPC分类号： H01L21/28 , H01L21/44 , H01L29/47 , H01L29/40 , H01L29/778 , H01L29/872 , H01L23/31 , H01L29/423 , H01L29/20
CPC分类号： H01L29/475 , H01L23/3171 , H01L23/3192 , H01L29/2003 , H01L29/401 , H01L29/42316 , H01L29/778 , H01L29/7786 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
摘要翻译：与示例性实施例一致，GaN异质结结构具有三层电介质结构。栅电极的最下部和中部一起限定栅极脚，并且这与两个电介质层相关联。较薄的第一介电层与栅极底部的栅极边缘相邻。第二电介质层对应于常规结构中的层，并且与栅极脚的主要部分平齐。

3. 发明授权

US09385226B2 Semiconductor heterojunction device 有权
标题翻译：半导体异质结装置
公开(公告)号：US09385226B2
公开(公告)日：2016-07-05
申请号：US14613182
申请日：2015-02-03
申请人： NXP B.V.
发明人： Johannes Josephus Theodorus Marinus Donkers , Godefridus Adrianus Maria Hurkx , Stephan Bastiaan Simon Heil , Michael Antoine Armand in 't Zandt
IPC分类号： H01L29/15 , H01L29/778 , H01L29/20 , H01L29/201 , H01L29/205 , H01L23/31 , H01L29/872 , H01L29/267 , H01L29/40
CPC分类号： H01L29/7787 , H01L23/3171 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/267 , H01L29/405 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device. The second terminal (212) is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal (212) from the semiconductor passivation layer (208).
摘要翻译：一种异质结半导体器件（200），包括衬底（202）和设置在衬底上的多层结构。所述多层结构包括第一层（204），其包括设置在所述衬底顶部上的第一半导体和第二层（206），所述第二层（206）包括设置在所述第一层顶部上以限定所述第一层层和第二层。第二半导体与第一半导体不同，使得邻近界面形成二维电子气（220）。多层结构还包括钝化层，其包括设置在第二层顶部上的半导体钝化层（208）。异质结半导体器件还包括电耦合到异质结半导体器件的第一区域的第一端子（210）以及电耦合到异质结半导体器件的第二区域的第二端子（212）。第二端子（212）电耦合到半导体钝化层，使得电荷可以从半导体钝化层（208）流入第二端子（212）。

4. 发明授权

US09305789B2 Semiconductor device comprising an active layer and a Schottky contact 有权
标题翻译：半导体器件包括有源层和肖特基接触
公开(公告)号：US09305789B2
公开(公告)日：2016-04-05
申请号：US14693118
申请日：2015-04-22
申请人： NXP B.V.
发明人： Johannes Josephus Theodorus Marinus Donkers , Stephan Bastiaan Simon Heil , Jos aan de Stegge
IPC分类号： H01L29/00 , H01L21/285 , H01L21/283 , H01L29/47 , H01L29/20
CPC分类号： H01L21/28581 , H01L21/283 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L2924/01022 , H01L2924/01074
摘要： A semiconductor device comprising at least one active layer on a substrate and a a Schottky contact to the at least one active layer, the Schottky contact comprising a body of at least titanium and nitrogen that is electrically coupled with the at least one active layer.
摘要翻译：一种半导体器件，其包括在衬底上的至少一个有源层和与所述至少一个有源层的肖特基接触，所述肖特基接触包括与所述至少一个有源层电耦合的至少钛和氮的主体。

5. 发明申请

US20150325667A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20150325667A1
公开(公告)日：2015-11-12
申请号：US14693118
申请日：2015-04-22
申请人： NXP B.V.
发明人： Johannes Josephus Theodorus Marinus Donkers , Stephan Bastiaan Simon Heil , Jos aan de Stegge
IPC分类号： H01L29/47 , H01L21/283
CPC分类号： H01L21/28581 , H01L21/283 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L2924/01022 , H01L2924/01074
摘要： A semiconductor device comprising at least one active layer on a substrate and a a Schottky contact to the at least one active layer, the Schottky contact comprising a body of at least titanium and nitrogen that is electrically coupled with the at least one active layer.
摘要翻译：一种半导体器件，其包括在衬底上的至少一个有源层和与所述至少一个有源层的肖特基接触，所述肖特基接触包括与所述至少一个有源层电耦合的至少钛和氮的主体。

6. 发明申请

US20130320400A1 HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译：异相半导体器件及制造方法
公开(公告)号：US20130320400A1
公开(公告)日：2013-12-05
申请号：US13895228
申请日：2013-05-15
申请人： NXP B.V.
发明人： Godefridus Adrianus Maria HURKX , Jeroen Antoon CROON , Johannes Josephus Theodorus Marinus Donkers , Jan Sonsky , Stephen John SQUE , Andreas Bernardus Maria JANSMAN , Markus MUELLER , Stephan HEIL , Tim BOETTCHER
IPC分类号： H01L29/47 , H01L29/40
CPC分类号： H01L29/475 , H01L21/02362 , H01L21/0254 , H01L29/2003 , H01L29/401 , H01L29/417 , H01L29/42316 , H01L29/7787 , H01L29/7788 , H01L29/872
摘要： Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.
摘要翻译：公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分用于局部增加肖特基电极的肖特基势垒。还公开了制造这种半导体器件的方法。

7. 发明授权

US11018230B1 Semiconductor devices with a mixed crystal region 有权
公开(公告)号：US11018230B1
公开(公告)日：2021-05-25
申请号：US16723311
申请日：2019-12-20
申请人： NXP B.V.
发明人： Tony Vanhoucke , Mahmoud Shehab Mohammad Al-Sa'di , Johannes Josephus Theodorus Marinus Donkers , Jan Willem Slotboom
IPC分类号： H01L29/165 , H01L29/737 , H01L29/868
摘要： An embodiment of a semiconductor device may include a semiconductor substrate, a first semiconductor region comprising a first material with a first polarity formed within the semiconductor substrate and a second semiconductor region comprising the first material with a second polarity formed within the semiconductor substrate and coupled to the first semiconductor region. In an embodiment, a semiconductor device may also include a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region, and a depletion region formed between the first semiconductor region and the second semiconductor region. The depletion region may include a mixed crystal region that includes a mixed crystal alloy of the first material and a second material, wherein the mixed crystal region has a lower bandgap energy than a bandgap energy of the first material.

8. 发明授权

US09431524B2 Method of manufacturing IC comprising a bipolar transistor and IC 有权
标题翻译：制造包括双极晶体管和IC的IC的方法
公开(公告)号：US09431524B2
公开(公告)日：2016-08-30
申请号：US14524365
申请日：2014-10-27
申请人： NXP B.V.
发明人： Johannes Josephus Theodorus Marinus Donkers , Petrus Hubertus Cornelis Magnee , Blandine Duriez , Evelyne Gridelet , Hans Mertens , Tony Vanhoucke
IPC分类号： H01L31/072 , H01L31/109 , H01L29/737 , H01L21/8249 , H01L29/66 , H01L27/06 , H01L29/10 , H01L29/161 , H01L29/165 , H01L29/45
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/161 , H01L29/165 , H01L29/456 , H01L29/66242
摘要： Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate (10) comprising a pair of first isolation regions (12) separated from each other by an active region (11) comprising a collector impurity said bipolar transistor; forming a base layer stack (14, 14′) over said substrate; forming a further stack of a migration layer (15) having a first migration temperature and an etch stop layer (20) over said base layer stack (14); forming a base contact layer (16) having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window (28) in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities (29) extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. An IC comprising such a bipolar transistor is also disclosed.
摘要翻译：公开了一种制造包括双极晶体管的集成电路的方法，所述方法包括提供包括一对第一隔离区（12）的衬底（10），所述第一隔离区（12）通过包含集电极杂质的有源区（11）彼此分离，所述有源区晶体管在所述衬底上形成基层叠层（14,14'）; 在所述基层堆叠（14）上方形成具有第一迁移温度和蚀刻停止层（20）的迁移层（15）的另一叠层; 形成具有超过另一堆叠的第二迁移温度的基底接触层（16），所述第二迁移温度高于所述第一迁移温度; 在所述有源区上蚀刻所述基极接触层中的发射极窗口（28），所述蚀刻步骤终止于所述蚀刻停止层; 至少部分地去除所述蚀刻停止层，从而形成从所述基底接触层和所述再分布层之间的所述发射窗延伸的空腔（29）并在氢气氛中将所得结构暴露于第一迁移温度，由此用迁移层材料填充空腔。还公开了包括这种双极晶体管的IC。

9. 发明授权

US09349819B2 Heterojunction semiconductor device and manufacturing method 有权
标题翻译：异质结半导体器件及其制造方法
公开(公告)号：US09349819B2
公开(公告)日：2016-05-24
申请号：US14714927
申请日：2015-05-18
申请人： NXP B.V.
发明人： Godefridus Adrianus Maria Hurkx , Jeroen Antoon Croon , Johannes Josephus Theodorus Marinus Donkers , Jan Sonsky , Stephen John Sque , Andreas Bernardus Maria Jansman , Markus Mueller , Stephan Heil , Tim Boettcher
IPC分类号： H01L29/20 , H01L21/02 , H01L29/47 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/872 , H01L29/40
CPC分类号： H01L29/475 , H01L21/02362 , H01L21/0254 , H01L29/2003 , H01L29/401 , H01L29/417 , H01L29/42316 , H01L29/7787 , H01L29/7788 , H01L29/872
摘要： Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.
摘要翻译：公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分用于局部增加肖特基电极的肖特基势垒。还公开了制造这种半导体器件的方法。

10. 发明授权

US08946042B2 Bipolar transistor manufacturing method, bipolar transistor and integrated circuit 有权
标题翻译：双极晶体管制造方法，双极晶体管和集成电路
公开(公告)号：US08946042B2
公开(公告)日：2015-02-03
申请号：US14177880
申请日：2014-02-11
申请人： NXP B.V.
发明人： Evelyne Gridelet , Johannes Josephus Theodorus Marinus Donkers , Tony Vanhoucke , Petrus Hubertus Cornelis Magnee , Hans Mertens , Blandine Duriez
IPC分类号： H01L29/72 , H01L29/732 , H01L29/66 , H01L29/737
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/7378
摘要： Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.
摘要翻译：公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10）在所述衬底上形成层堆叠，所述层堆叠包括在所述基底层上方的基底层（14,14'），硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基底接触层（40）盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

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