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1. 发明授权

US09406374B1 Mitigating leakage in memory circuits 有权
标题翻译：缓解内存电路中的漏电
公开(公告)号：US09406374B1
公开(公告)日：2016-08-02
申请号：US14882206
申请日：2015-10-13
申请人： NXP B.V.
发明人： Jainendra Singh , Pankaj Agarwal , Patrick van de Steeg , Jwalant Kumar Mishra
IPC分类号： G11C11/00 , G11C11/419 , G11C11/418
CPC分类号： G11C11/418 , G11C8/08
摘要： An apparatus includes a memory circuit and a word-line driver circuit. The memory circuit includes a plurality of rows of memory cells, each memory cell in a corresponding row having pass transistors connected to a shared word-line. The word-line driver circuit is configured and arranged to enable pass transistors of a first set of memory cells of the memory circuit by applying a first voltage to word-lines of the first set of memory cells, disable pass transistors of a second set of memory cells of the memory circuit by applying a second voltage to word-lines of the second set of memory cells, and mitigate leakage of pass transistors of a third set of memory cells of the memory circuit by applying a third voltage to word-lines of the third set of memory cells, wherein the third voltage is between the first and second voltages.
摘要翻译：一种装置包括存储电路和字线驱动电路。存储电路包括多行存储单元，相应行中的每个存储单元具有连接到共享字线的传输晶体管。字线驱动器电路被配置和布置成通过对第一组存储器单元的字线施加第一电压来使能存储器电路的第一组存储单元的通过晶体管，禁用第二组存储器单元的字线通过对第二组存储器单元的字线施加第二电压并且通过将第三电压施加到存储器电路的字线来减轻存储器电路的第三组存储器单元的传输晶体管的泄漏来减轻存储器电路的存储单元第三组存储器单元，其中第三电压在第一和第二电压之间。

2. 发明授权

US09202588B1 1T compact ROM cell with dual bit storage for high speed and low voltage 有权
标题翻译： 1T紧凑的ROM单元，具有双位存储，适用于高速和低电压
公开(公告)号：US09202588B1
公开(公告)日：2015-12-01
申请号：US14494263
申请日：2014-09-23
申请人： NXP B.V.
发明人： Rajat Kohli , Patrick Van de steeg , Jwalant Mishra , Pankaj Agarwal
IPC分类号： G11C17/00 , G11C17/12
CPC分类号： G11C17/12 , G11C11/5692 , G11C17/126
摘要： Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.
摘要翻译：公开了一种ROM存储器件，其包括存储单元的多个行和列，每个存储单元包括位线对和晶体管，用于在其中存储两位数据，以及设置在相邻的位线对对之间的虚拟接地线，其中位线对和虚拟接地线用于读取存储在存储单元中的数据。

3. 发明申请

US20190080777A1 DUAL-BIT ROM CELL WITH VIRTUAL GROUND LINE AND PROGRAMMABLE METAL TRACK 审中-公开
公开(公告)号：US20190080777A1
公开(公告)日：2019-03-14
申请号：US15700152
申请日：2017-09-10
申请人： NXP B.V.
发明人： Rajat Kohli , Patrick Van de Steeg , Jwalant Kumar Mishra , Pankaj Agarwal
IPC分类号： G11C17/12 , G11C11/56 , G11C11/40
摘要： A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

4. 发明授权

US09691496B1 High density ROM cell with dual bit storage for high speed and low voltage 有权
公开(公告)号：US09691496B1
公开(公告)日：2017-06-27
申请号：US15018194
申请日：2016-02-08
申请人： NXP B.V.
发明人： Rajat Kohli , Patrick van de Steeg , Jwalant Kumar Mishra , Pankaj Agarwal
IPC分类号： G11C17/00 , G11C17/12
CPC分类号： G11C17/126 , G11C11/5692 , G11C17/12
摘要： Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.

5. 发明授权

US10236071B1 Dual-bit ROM cell with virtual ground line and programmable metal track 有权
公开(公告)号：US10236071B1
公开(公告)日：2019-03-19
申请号：US15700152
申请日：2017-09-10
申请人： NXP B.V.
发明人： Rajat Kohli , Patrick Van De Steeg , Jwalant Kumar Mishra , Pankaj Agarwal
IPC分类号： G11C17/12 , G11C11/40 , G11C11/56
摘要： A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

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