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1. 发明申请

US20230066987A1 SELF CALIBRATING DIGITAL-TO-ANALOG CONVERTER 有权
公开(公告)号：US20230066987A1
公开(公告)日：2023-03-02
申请号：US17819092
申请日：2022-08-11
申请人： NXP USA, INC.
发明人： Yizhong Zhang , Jie Jin , Stefano Pietri , Michael Todd Berens , Hongyan Yao , Jiawei Fu
IPC分类号： H03M1/10
摘要： A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

2. 发明授权

US11588495B2 Analog front-end circuit capable of use in a sensor system 有权
公开(公告)号：US11588495B2
公开(公告)日：2023-02-21
申请号：US17305627
申请日：2021-07-12
申请人： NXP USA, Inc.
发明人： Stefano Pietri , Michael Todd Berens , Yikun Mo , Ashutosh Jain
IPC分类号： H03M1/00 , H03M3/00 , A61B5/00
摘要： During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

3. 发明申请

US20230031469A1 DIGITAL TO ANALOG CONVERTER 有权
公开(公告)号：US20230031469A1
公开(公告)日：2023-02-02
申请号：US17812542
申请日：2022-07-14
申请人： NXP USA, Inc.
发明人： Yizhong Zhang , Stefano Pietri , Jie Jin , Michael Todd Berens
IPC分类号： H03M1/68 , H03M1/78
摘要： A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.

4. 发明授权

US10243577B1 Analog-to-digital converter (ADC) having calibration 有权
公开(公告)号：US10243577B1
公开(公告)日：2019-03-26
申请号：US15943173
申请日：2018-04-02
申请人： NXP USA, INC.
发明人： Michael Todd Berens , Khoi Mai , James Robert Feddeler
IPC分类号： H03M1/20 , H03M1/10
摘要： An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage. The ADC includes a comparator coupled to receive the output voltage, successive-approximation-register (SAR) circuitry coupled to the comparator and providing an uncalibrated digital value corresponding to an uncalibrated digital representation of the input voltage, and calibration circuitry configured to apply one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital.

5. 发明申请

US20190372586A1 SEGMENTED RESISTIVE DIGITAL TO ANALOG CONVERTER 审中-公开
公开(公告)号：US20190372586A1
公开(公告)日：2019-12-05
申请号：US16237724
申请日：2019-01-01
申请人： NXP USA, INC.
发明人： Yizhong Zhang , Stefano Pietri , James Robert Feddeler , Michael Todd Berens
IPC分类号： H03M1/68 , H03M7/16 , H03M1/74 , H03M1/78
摘要： A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

6. 发明授权

US10110244B1 Digital to analog converter (DAC) having sub-DACs with arrays of resistors 有权
公开(公告)号：US10110244B1
公开(公告)日：2018-10-23
申请号：US15834559
申请日：2017-12-07
申请人： NXP USA, INC.
发明人： Stefano Pietri , James Robert Feddeler , Michael Todd Berens , Yizhong Zhang
IPC分类号： H03M1/66 , H03M1/68
摘要： A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.

7. 发明授权

US10790848B2 Segmented resistive digital to analog converter 有权
公开(公告)号：US10790848B2
公开(公告)日：2020-09-29
申请号：US16237724
申请日：2019-01-01
申请人： NXP USA, INC.
发明人： Yizhong Zhang , Stefano Pietri , James Robert Feddeler , Michael Todd Berens
IPC分类号： H03M1/66 , H03M1/68 , H03M1/74 , H03M1/78 , H03M7/16
摘要： A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

8. 发明授权

US10784886B1 Segmented digital to analog converter 有权
公开(公告)号：US10784886B1
公开(公告)日：2020-09-22
申请号：US16797096
申请日：2020-02-21
申请人： NXP USA, Inc.
发明人： Yizhong Zhang , Stefano Pietri , James Robert Feddeler , Michael Todd Berens
IPC分类号： H03M1/66 , H03M1/68 , H03M1/76 , H03M1/78 , H03M1/80 , H03M1/00
摘要： A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

9. 发明授权

US10295572B1 Voltage sampling switch 有权
公开(公告)号：US10295572B1
公开(公告)日：2019-05-21
申请号：US15951414
申请日：2018-04-12
申请人： NXP USA, INC.
发明人： Khoi Mai , Michael Todd Berens , Jon Scott Choy
IPC分类号： H03K5/00 , G01R15/16 , G01R19/00 , H03K17/08 , H03K5/24
摘要： A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.

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