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1. 发明授权

US08921912B2 Nonvolatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08921912B2
公开(公告)日：2014-12-30
申请号：US13402989
申请日：2012-02-23
申请人： Nam-Jae Lee , Seiichi Aritome
发明人： Nam-Jae Lee , Seiichi Aritome
IPC分类号： H01L29/788 , H01L29/66 , H01L27/115
CPC分类号： H01L21/76224 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.
摘要翻译：非易失性存储器件包括具有由隔离层限定的并且具有从隔离层向上延伸的第一侧壁的有源区的衬底，与有源区相邻的浮动栅极与介于有源区之间的隧道介电层和浮置栅极并从衬底向上延伸，布置在浮置栅极上的隔间介电层以及设置在栅极间介电层上的控制栅极。

2. 发明申请

US20120241840A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120241840A1
公开(公告)日：2012-09-27
申请号：US13402989
申请日：2012-02-23
申请人： Nam-Jae Lee , Seiichi Aritome
发明人： Nam-Jae Lee , Seiichi Aritome
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/76224 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.
摘要翻译：非易失性存储器件包括具有由隔离层限定的并且具有从隔离层向上延伸的第一侧壁的有源区的衬底，与有源区相邻的浮动栅极与介于有源区之间的隧道介电层和浮置栅极并从衬底向上延伸，布置在浮置栅极上的隔间介电层以及设置在栅极间介电层上的控制栅极。

3. 发明授权

US08530309B2 Memory device and method for fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08530309B2
公开(公告)日：2013-09-10
申请号：US13597141
申请日：2012-08-28
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L21/8247
CPC分类号： H01L27/11524 , H01L21/76897 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings.
摘要翻译：一种用于形成存储器件的方法包括：在衬底上形成隧道绝缘层，浮栅电极用导电层，电荷阻挡层和控制栅电极用导电层; 并且选择性地蚀刻用于控制栅电极的导电层，电荷阻挡层和用于浮置栅电极的导电层，由此形成多个栅极线，多条选择线和至少两条设置在间隙区域中的虚设线在相邻选择线之间，其中栅极线，选择线和虚线一起构成串。

4. 发明授权

US07129131B2 Method for fabricating capacitor of semiconductor device 有权
标题翻译：制造半导体器件电容器的方法
公开(公告)号：US07129131B2
公开(公告)日：2006-10-31
申请号：US10741787
申请日：2003-12-18
申请人： Nam-Jae Lee , Kye-Soon Park
发明人： Nam-Jae Lee , Kye-Soon Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/76877 , H01L27/10817 , H01L27/10855 , H01L28/60
摘要： A method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer. The spacer is formed along a profile containing the bit line and the hard mask. A first inter-layer insulation layer is deposited on an entire surface of the bit line structure. A storage node contact plug is formed on the substrate by passing through the inter-layer insulation layer and having a partially etched portion. A second inter-layer insulation layer is formed on a partial portion of the first inter-layer insulation layer and the storage node contact plug. A lower electrode having a circular shape is formed on lateral sides of the second inter-layer insulation layer, an exposed portion of the first inter-layer insulation layer and the partially etched portion of the storage node contact plug, wherein the lower electrode electrically contacts at least a predetermined lateral side of the partially etched portion.
摘要翻译：一种制造半导体器件的电容器的方法。半导体器件包括：形成在衬底上并包括位线，硬掩模和间隔物的层叠层的位线结构。间隔物沿着包含位线和硬掩模的轮廓形成。第一层间绝缘层沉积在位线结构的整个表面上。通过穿过层间绝缘层并具有部分蚀刻的部分，在基板上形成存储节点接触插塞。在第一层间绝缘层和存储节点接触插塞的部分部分上形成第二层间绝缘层。具有圆形形状的下电极形成在第二层间绝缘层的横向侧，第一层间绝缘层的露出部分和存储节点接触插塞的部分蚀刻部分，其中下电极电接触至少部分蚀刻部分的预定侧面。

5. 发明授权

US09165939B2 Method for fabricating nonvolatile memory device 有权
标题翻译：非易失性存储器件的制造方法
公开(公告)号：US09165939B2
公开(公告)日：2015-10-20
申请号：US13606495
申请日：2012-09-07
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L21/8238 , H01L21/76 , H01L21/3205 , H01L21/4763 , H01L27/115 , H01L27/06
CPC分类号： H01L27/11546 , H01L27/0629 , H01L27/11529
摘要： A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.
摘要翻译：一种制造非易失性存储器件的方法包括在包括第一区域和第二区域的衬底上形成第一绝缘层和第一导电层，通过蚀刻第一导电层在第一区域中形成第一隔离沟槽，第一绝缘层层和衬底，形成填充在第一隔离沟槽中的第一隔离层，形成第二绝缘层和导电覆盖层，蚀刻覆盖层和第二绝缘层，形成第二导电层，以及形成第一栅极图案通过蚀刻第二导电层，覆盖层，第二绝缘层，第一导电层和第一区域的第一绝缘层，并且通过蚀刻第二导电层在第二区域中形成第二隔离沟槽，第一导电层导电层，第一绝缘层和基板。

6. 发明授权

US08513076B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08513076B2
公开(公告)日：2013-08-20
申请号：US13472969
申请日：2012-05-16
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L27/11529 , H01L27/11521
摘要： A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
摘要翻译：非易失性存储器件包括外围电路区域和单元区域。一种用于制造非易失性存储器件的方法包括在衬底上形成栅极图案，栅极图案包括隧道绝缘层，浮栅电极，电荷阻挡层和控制栅电极，以及去除控制栅极和形成在外围电路区域中的栅极图案的电荷阻挡层。

7. 发明授权

US07763524B2 Method for forming isolation structure of different widths in semiconductor device 失效
标题翻译：在半导体器件中形成不同宽度的隔离结构的方法
公开(公告)号：US07763524B2
公开(公告)日：2010-07-27
申请号：US11823774
申请日：2007-06-28
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L27/1052 , H01L27/115 , H01L27/11526 , H01L27/11531
摘要： A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, is provided. The method includes etching portions of the first and second regions of the substrate to form first and second trenches, wherein a width of the second trench is larger than that of the first trench, forming a first insulation layer to fill a portion of the first and second trenches, forming a barrier layer to fill the first and second trenches, etching portions of the first insulation layer and the barrier layer in the first region, removing the barrier layer, and forming a second insulation layer over the first insulation layer.
摘要翻译：提供一种用于在包括具有第一区域和第二区域的基板的半导体器件中形成隔离结构的方法，所述第二区域具有形成为比形成在第一区域中的多个隔离结构更大的宽度的隔离结构。该方法包括蚀刻衬底的第一和第二区域的部分以形成第一和第二沟槽，其中第二沟槽的宽度大于第一沟槽的宽度，形成第一绝缘层以填充第一和第二沟槽的一部分，第二沟槽，形成阻挡层以填充第一和第二沟槽，蚀刻第一区域中的第一绝缘层和阻挡层的部分，去除阻挡层，以及在第一绝缘层上形成第二绝缘层。

8. 发明授权

US07332761B2 Method for fabricating capacitor of semiconductor device 有权
标题翻译：制造半导体器件电容器的方法
公开(公告)号：US07332761B2
公开(公告)日：2008-02-19
申请号：US11351450
申请日：2006-02-09
申请人： Nam-Jae Lee , Kye-Soon Park
发明人： Nam-Jae Lee , Kye-Soon Park
IPC分类号： H01L29/76
CPC分类号： H01L28/91 , H01L21/76877 , H01L27/10817 , H01L27/10855 , H01L28/60
摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer, the spacer formed along a profile containing the bit line and the hard mask; a first inter-layer insulation layer deposited on an entire surface of the bit line structure; a storage node contact plug formed on the substrate by passing through the inter-layer insulation layer and having a partially etched portion; a second inter-layer insulation layer formed on a partial portion of the first inter-layer insulation layer and the storage node contact plug; and a lower electrode having a circular shape and formed on lateral sides of the second inter-layer insulation layer, an exposed portion of the first inter-layer insulation layer and the partially etched portion of the storage nod contact plug, wherein the lower electrode electrically contacted at least with a predetermined lateral side of the partially etched portion.
摘要翻译：本发明涉及半导体器件的电容器的制造方法。半导体器件包括：形成在衬底上并包括位线，硬掩模和间隔物的叠层的位线结构，沿着包含位线和硬掩模的轮廓形成的间隔件; 沉积在所述位线结构的整个表面上的第一层间绝缘层; 存储节点接触插塞，其通过穿过所述层间绝缘层并且具有部分蚀刻部分而形成在所述基板上; 形成在第一层间绝缘层和存储节点接触插塞的部分部分上的第二层间绝缘层; 以及形成在第二层间绝缘层的侧面上的圆形形状的下电极，第一层间绝缘层的露出部分和存储点头接触插塞的部分蚀刻部分，其中电极电至少与部分蚀刻部分的预定侧面接触。

9. 发明授权

US09685451B2 Nonvolatile memory device and method for fabricating the same 有权
公开(公告)号：US09685451B2
公开(公告)日：2017-06-20
申请号：US13610785
申请日：2012-09-11
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L29/788 , H01L27/11524
CPC分类号： H01L27/11524
摘要： A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.

10. 发明授权

US08253185B2 Memory device and method for fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08253185B2
公开(公告)日：2012-08-28
申请号：US12413427
申请日：2009-03-27
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L21/76897 , H01L27/11521 , H01L27/11568
摘要： A memory device includes gate lines and select lines formed over a substrate, and at least two dummy lines formed in a gap region between adjacent select lines. The memory device is able to reduce a width of the select line by enhancing uniformity of the line pattern density. Therefore, a degree of integration of the memory device is enhanced and the cost of production is reduced. Furthermore, by forming a source line in a gap region between adjacent dummy lines, it is possible to secure a process margin of photolithography for forming a contact hole and to reduce contact resistance.
摘要翻译：存储器件包括形成在衬底上的栅极线和选择线，以及形成在相邻选择线之间的间隙区域中的至少两条虚线。存储器件能够通过增强线图案密度的均匀性来减小选择线的宽度。因此，提高了存储装置的集成度，降低了生产成本。此外，通过在相邻虚拟线之间的间隙区域中形成源极线，可以确保用于形成接触孔的光刻的工艺余量并降低接触电阻。

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