专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20230128785A1 Body-Source-Tied Transistor 有权
公开(公告)号：US20230128785A1
公开(公告)日：2023-04-27
申请号：US18085930
申请日：2022-12-21
申请人： Newport Fab, LLC dba Jazz Semiconductor
发明人： Allan K. Calvo , Paul D. Hurwitz , Roda Kanawati
IPC分类号： H01L21/762 , H01L27/12 , H01L29/49 , H01L23/66
摘要： A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

2. 发明申请

US20200058706A1 Stacked Phase-Change Material (PCM) Radio Frequency (RF) Switches with Improved RF Power Handling 审中-公开
公开(公告)号：US20200058706A1
公开(公告)日：2020-02-20
申请号：US16188782
申请日：2018-11-13
申请人： Newport Fab, LLC dba Jazz Semiconductor
发明人： Nabil El-Hinnawy , Paul D. Hurwitz , Gregory P. Slovin , Jefferson E. Rose , Roda Kanawati , David J. Howard
IPC分类号： H01L27/24 , H01L45/00
摘要： A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.

3. 发明申请

US20190109055A1 HIGH PERFORMANCE SiGe HETEROJUNCTION BIPOLAR TRANSISTORS BUILT ON THIN-FILM SILICON-ON-INSULATOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS 审中-公开
公开(公告)号：US20190109055A1
公开(公告)日：2019-04-11
申请号：US16026006
申请日：2018-07-02
申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.
发明人： Edward J. Preisler , Paul D. Hurwitz , Marco Racanelli , David J. Howard
IPC分类号： H01L21/84 , H01L27/06 , H01L27/12 , H01L29/737 , H01L21/8249 , H01L29/66 , H01L29/165
摘要： A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

4. 发明申请

US20180323757A1 HIGH POWER RF SWITCHES USING MULTIPLE OPTIMIZED TRANSISTORS 审中-公开
公开(公告)号：US20180323757A1
公开(公告)日：2018-11-08
申请号：US16025996
申请日：2018-07-02
申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.
发明人： Paul D. Hurwitz , Roda Kanawati
IPC分类号： H03F3/24 , H01L21/84 , H01L27/12 , H01L29/10 , H01L29/78 , H03K17/10
摘要： An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

5. 发明授权

US09966301B2 Reduced substrate effects in monolithically integrated RF circuits 有权
公开(公告)号：US09966301B2
公开(公告)日：2018-05-08
申请号：US15193598
申请日：2016-06-27
申请人： Newport Fab, LLC
发明人： David J. Howard , Michael J. DeBar , Paul D. Hurwitz
IPC分类号： H01L21/30 , H01L21/46 , H01L21/00 , H01L21/762 , H01L21/304 , H01L21/306 , H01L23/367 , H01L23/373 , H01L21/84
CPC分类号： H01L21/76251 , H01L21/304 , H01L21/30604 , H01L21/84 , H01L23/367 , H01L23/3731 , H01L2224/05025
摘要： A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.

6. 发明授权

US09917104B1 Hybrid MOS-PCM CMOS SOI switch 有权
公开(公告)号：US09917104B1
公开(公告)日：2018-03-13
申请号：US15627261
申请日：2017-06-19
申请人： Tower Semiconductor Ltd. , Newport Fab, LLC
发明人： Yakov Roizin , David J. Howard , Paul D. Hurwitz
IPC分类号： H04B1/04 , H01L27/12 , H01L29/06 , H01L45/00
CPC分类号： H01L27/1203 , H01L29/0649 , H01L29/0676 , H01L45/06 , H04B1/0483
摘要： A hybrid MOS-PCM IC switch utilizes both MOS transistors and groups of parallel-connected Phase-Change Material (PCM) cells to control signal transmissions. The MOS transistors are separated by PCM cell groups, and the PCM cells are configured to generate similar COFF or lower values as the MOS transistors, whereby the hybrid switch is both smaller and exhibits lower FOM than standard CMOS SOI switches. When switched into an open (OFF/high-resistance) state, both the PCM cells and MOS transistors function to distribute high VBSR voltages, and the MOS transistors prevent unintended phase changes (ON/OFF switching) of the PCM cells by preventing exponential current flow. In the closed (ON/conducting) state, the PCM cells facilitate lower total RON, whereby the hybrid CMOS SOI switch achieves improved FOM. The MOS transistors may also function as drivers during programming (switching) of direct-heating-type PCM cells.

7. 发明申请

US20170338321A1 NICKEL SILICIDE IMPLEMENTATION FOR SILICON-ON-INSULATOR (SOI) RADIO FREQUENCY (RF) SWITCH TECHNOLOGY 审中-公开
公开(公告)号：US20170338321A1
公开(公告)日：2017-11-23
申请号：US15158514
申请日：2016-05-18
申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.
发明人： Paul D. Hurwitz , Kurt Moen
IPC分类号： H01L29/45 , H03K17/687 , H01L29/786 , H01L29/66 , H01L29/417 , H01L21/285 , H01L29/40 , H01L27/12 , H01L21/768 , H01L21/3105 , H04B1/38 , H01L29/423
CPC分类号： H01L29/458 , H01L21/28518 , H01L21/2855 , H01L21/76843 , H01L27/1222 , H01L29/401 , H01L29/41733 , H01L29/42384 , H01L29/665 , H01L29/66772 , H01L29/78654 , H03K17/102 , H03K17/6872 , H03K17/693 , H04B1/38 , H04B1/48
摘要： A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger) process, wherein the SOI CMOS transistors include nickel silicide formed on the source/drain regions. Each of the series-connected SOI CMOS transistors has a gate length of about 0.13 microns or more, thereby enabling these SOI CMOS transistors to handle high power RF signals, and exhibit the high breakdown voltages required to implement an RF switch. The nickel silicide regions advantageously contribute to a relatively a low on-resistance (RON) of the SOI CMOS transistors, while consuming a relatively small amount of the underlying silicon regions during their fabrication. The SOI CMOS transistors can be fabricated on a relatively thin silicon layer, thereby contributing to a relatively low off capacitance (COFF) of the SOI CMOS transistors. As a result, an RON*COFF value of the RF switch is advantageously minimized.

8. 发明授权

US09620617B2 Structure and method for reducing substrate parasitics in semiconductor on insulator technology 有权
公开(公告)号：US09620617B2
公开(公告)日：2017-04-11
申请号：US14827183
申请日：2015-08-14
申请人： Newport Fab, LLC
发明人： Paul D. Hurwitz
IPC分类号： H01L21/762 , H01L29/06 , H01L27/12 , H01L29/66 , H01L21/84 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66477 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78 , H01L29/786
摘要： A structure having improved electrical signal isolation and linearity is disclosed. The structure includes a buried oxide (“BOX”) layer over a bulk semiconductor layer, a device layer over the buried oxide layer, a compensation implant region near an interface of the buried oxide layer and the bulk semiconductor layer, wherein the compensation implant region is configured to substantially eliminate a parasitic conduction layer near the buried oxide layer. The compensation implant region has a doping concentration of at least one order of magnitude higher than a doping concentration of the bulk semiconductor layer. The structure includes a deep trench extending through the device layer and the buried oxide layer, and a damaged implant region in the bulk semiconductor layer near the deep trench. The structure also includes at least one transistor in the device layer.

9. 发明授权

US08956949B2 Electrical signal isolation in semiconductor structures 有权
标题翻译：半导体结构中的电信号隔离
公开(公告)号：US08956949B2
公开(公告)日：2015-02-17
申请号：US14465766
申请日：2014-08-21
申请人： Newport Fab, LLC
发明人： Paul D. Hurwitz , Robert L. Zwingman
IPC分类号： H01L21/322 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/76289 , H01L21/84
摘要： Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
摘要翻译：公开了一种用于在位于该结构的顶部半导体层中的相邻器件之间的电信号隔离的结构以及用于该结构的制造的相关方法。该结构包括延伸穿过顶部半导体层并在顶部半导体层下方的基底氧化物层中的沟槽。处理晶片位于基底氧化物层下方，并且在沟槽下方的手柄晶片中设置空隙。沟槽的底部开口将沟槽的主体与形成包括主体，沟槽的底部开口和空隙的连续空腔的空隙相连接，使得空隙改善了位于所述沟槽中的相邻装置之间的电信号隔离顶部半导体层。然后处理晶片的未蚀刻部分可用于向顶部半导体层提供机械支撑。

10. 发明申请

US20140252535A1 Integrated Passive Device Having Improved Linearity and Isolation 有权
标题翻译：具有改进的线性和隔离的集成被动设备
公开(公告)号：US20140252535A1
公开(公告)日：2014-09-11
申请号：US14165868
申请日：2014-01-28
申请人： Newport Fab, LLC dba Jazz Semiconductor
发明人： Paul D. Hurwitz
IPC分类号： H01L21/762 , H01L29/06 , H01L49/02
CPC分类号： H01L21/762 , H01L27/016
摘要： Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device.
摘要翻译：公开了一种用于在集成无源器件（IPD）之间的半导体衬底中改善电信号隔离的结构以及用于结构制造的相关方法。该结构包括半导体衬底中的非晶化区域，在非晶化区域上形成的电介质层，以及形成在电介质层上的IPD。非晶化区域不再结晶，并且可以通过利用不对非晶化区域进行电荷的惰性注入而形成，同时在非晶化区域和电介质层之间的界面处形成多个电荷载流子阱，以防止寄生导电层从界面形成。惰性植入物可以包括氩，氙和锗中的一种。在许多实现中，该结构不包括有源设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式