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1. 发明授权

US08736334B2 Current mode logic latch 有权
标题翻译：电流模式逻辑锁存
公开(公告)号：US08736334B2
公开(公告)日：2014-05-27
申请号：US13495786
申请日：2012-06-13
申请人： Shuo-Chun Kao , Nikola Nedovic
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03K3/356
CPC分类号： H03K3/356 , H03K3/0233 , H03K3/356043
摘要： A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
摘要翻译：电流模式逻辑锁存器可以包括在其漏极端子耦合到第一采样级晶体管的漏极端子的第一保持级晶体管。第二保持级晶体管在其漏极端子耦合到第二采样级晶体管的漏极端子，其栅极端子耦合到第一保持级晶体管的漏极端子，并在其漏极端子耦合到栅极端子第一级保持晶体管。第一保持级电流源耦合到第一保持级晶体管的源极端子。第二保持级电流源耦合到第二保持级晶体管的源极端。保持级开关耦合在第一保持级晶体管的源极端子和第二保持级晶体管的源极端子之间。

2. 发明申请

US20120023380A1 ALGORITHMIC MATCHING OF A DESKEW CHANNEL 有权
标题翻译： DESKEW频道的算法匹配
公开(公告)号：US20120023380A1
公开(公告)日：2012-01-26
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
IPC分类号： G06F11/07
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译：在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位数据位。

3. 发明授权

US08090064B2 Single loop frequency and phase detection 有权
标题翻译：单回路频率和相位检测
公开(公告)号：US08090064B2
公开(公告)日：2012-01-03
申请号：US12022725
申请日：2008-01-30
申请人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
发明人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译：在一个实施例中，一种方法包括接收包括多个比特的数据信号。该方法还包括产生时钟信号。从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点样品。如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。

4. 发明申请

US20100085086A1 Digital Frequency Detector 审中-公开
标题翻译：数字频率检测器
公开(公告)号：US20100085086A1
公开(公告)日：2010-04-08
申请号：US12510211
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H03B19/00
CPC分类号： H03L7/091 , H03L7/099 , H03L7/10 , H03L2207/06 , H04L7/033
摘要： In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.
摘要翻译：在一个实施例中，描述了一种包括接收第一时钟信号和第二时钟信号的方法; 将第一时钟信号除以n的值以产生分割的第一时钟信号; 对所述分频的第一时钟信号与所述第二时钟信号对所述频率检测器进行采样以产生多个采样; 如果一组连续样本中多于一个预定数量的连续样本具有相同的逻辑值，则产生第一调整信号; 以及如果小于所述连续样本集合中的预定数量的连续样本具有相同的逻辑值，则产生第二调整信号。

5. 发明授权

US07629817B2 System and apparatus for aperture time improvement 有权
标题翻译：孔径时间改进的系统和装置
公开(公告)号：US07629817B2
公开(公告)日：2009-12-08
申请号：US11960290
申请日：2007-12-19
申请人： Nikola Nedovic , William W. Walker
发明人： Nikola Nedovic , William W. Walker
IPC分类号： G01R19/00
CPC分类号： H03K3/356139 , H03K17/6871
摘要： In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
摘要翻译：在具体实施例中，一种装置包括在栅极处连接到第一输入信号电压的第一晶体管和在栅极处连接到第二输入信号电压的第二晶体管。该装置还包括耦合到晶体管的去激活元件，去激活元件可操作以通过选择性地将去激活电流传输到第一晶体管的第一端子和第二晶体管的第二端子而使第一和第二晶体管去激活，从而提高电压在第一和第二端子上达到足够大以使第一和第二晶体管去激活的值。在特定实施例中，激活第一或第二晶体管传输来自装置的信号，并且去激活第一和第二晶体管防止信号从装置传输。

6. 发明申请

US20080191770A1 System and Apparatus for Aperature Time Improvement 有权
标题翻译：高温时间改进系统和装置
公开(公告)号：US20080191770A1
公开(公告)日：2008-08-14
申请号：US11960290
申请日：2007-12-19
申请人： Nikola Nedovic , William W. Walker
发明人： Nikola Nedovic , William W. Walker
IPC分类号： H03K3/356 , H03K17/687
CPC分类号： H03K3/356139 , H03K17/6871
摘要： In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
摘要翻译：在具体实施例中，一种装置包括在栅极处连接到第一输入信号电压的第一晶体管和在栅极处连接到第二输入信号电压的第二晶体管。该装置还包括耦合到晶体管的去激活元件，去激活元件可操作以通过选择性地将去激活电流传输到第一晶体管的第一端子和第二晶体管的第二端子而使第一和第二晶体管去激活，从而提高电压在第一和第二端子上达到足够大以使第一和第二晶体管去激活的值。在特定实施例中，激活第一或第二晶体管传输来自装置的信号，并且去激活第一和第二晶体管防止信号从装置传输。

7. 发明授权

US07027345B2 Conditional pre-charge method and system 有权
公开(公告)号：US07027345B2
公开(公告)日：2006-04-11
申请号：US10043933
申请日：2002-01-11
申请人： Nikola Nedovic , Vojin G. Oklobd{hacek over (z)}ija , William W. Walker
发明人： Nikola Nedovic , Vojin G. Oklobd{hacek over (z)}ija , William W. Walker
IPC分类号： G11C7/00
CPC分类号： G06F1/32
摘要： Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.

8. 发明授权

US09025702B2 Method and apparatus for implementing slice-level adjustment 有权
标题翻译：用于实现切片级调整的方法和装置
公开(公告)号：US09025702B2
公开(公告)日：2015-05-05
申请号：US13219490
申请日：2011-08-26
申请人： Scott McLeod , Nikola Nedovic
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H04L25/10 , H04B10/69 , H04L7/00 , H04L7/033
CPC分类号： H04B10/695 , H04L7/0087 , H04L7/033
摘要： In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.
摘要翻译：在一个实施例中，接收机可以从发射机接收信号。接收机可以包括当信号的值为零时可以对信号进行采样的第一采样器。接收机还可以包括第二采样器，其可以在第一采样器对信号进行采样的时间与第一采样器对信号进行采样以产生一组采样值的下一次之间的中间采样信号。如果采样值大于参考电压的值，则接收机可以进一步可操作以确定采样值集合中的采样值为逻辑1，并且如果采样值较小，采样值为逻辑0 比参考电压的值。

9. 发明授权

US08680919B2 Impedance adjustments in amplifiers 有权
标题翻译：放大器阻抗调整
公开(公告)号：US08680919B2
公开(公告)日：2014-03-25
申请号：US13429206
申请日：2012-03-23
申请人： Scott McLeod , Nikola Nedovic
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H03F3/68
CPC分类号： H03F1/34 , H03F3/082
摘要： A circuit that includes an amplifier circuit with an input impedance due to an input resistance and an input capacitance of the amplifier circuit. The input impedance of the amplifier circuit may vary with frequency. The amplifier circuit may include an amplifier and a feedback circuit configured to provide feedback to the amplifier and to maintain the input impedance at a specified value at a selected frequency by increasing the input resistance of the amplifier circuit at the selected frequency.
摘要翻译：包括由输入电阻和放大器电路的输入电容引起的输入阻抗的放大器电路的电路。放大器电路的输入阻抗可能随频率而变化。放大器电路可以包括放大器和反馈电路，其被配置为向放大器提供反馈并且通过增加所选频率处的放大器电路的输入电阻将输入阻抗保持在选定频率处的指定值。

10. 发明申请

US20130188657A1 Automatic Synchronization of a Transmitter 有权
标题翻译：发射机的自动同步
公开(公告)号：US20130188657A1
公开(公告)日：2013-07-25
申请号：US13355202
申请日：2012-01-20
申请人： Nikola Nedovic , Shuo-Chun Kao
发明人： Nikola Nedovic , Shuo-Chun Kao
IPC分类号： H04L7/04 , H04J3/06
CPC分类号： H03M9/00 , H04J3/0685
摘要： An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.
摘要翻译：电子设备包括通信地耦合到同步器的传输模块。发送模块被配置为转换接收的数据进行发送，基于指令调整用于对接收数据进行变换的时间信号的相位的指令，从同步器接收第一指令，并将调整后的时钟信号发送到同步器。同步器被配置为接收经调整的时钟信号，基于经调整的时钟信号和数据信号接收包括要发送的数据的频率和相位的数据信号，确定传输模块的第二指令，并提供传输模块的第二条指令。

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