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    • 2. 发明授权
    • Modeling gate resistance of a multi-fin multi-gate field effect transistor
    • 多鳍多栅极场效应晶体管的栅极电阻建模
    • US09043192B2
    • 2015-05-26
    • US13462849
    • 2012-05-03
    • Ning Lu
    • Ning Lu
    • G06F17/50
    • G06F17/5022G06F17/5036G06F2217/82
    • The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.
    • 实施例涉及多鳍多栅极场效应晶体管(MUGFET)中的建模电阻。 在这些实施例中,多翅片MUGFET的设计包括具有横穿多个半导体鳍片的水平部分并且包括串联连接的多个第一电阻元件的栅极结构,其中与半导体鳍片的相对侧相邻的垂直部分包括第二 电阻元件由水平部分并联连接,并具有包括第三电阻元件的接触件。 基于来自第一电阻元件,第二电阻元件和第三电阻元件的电阻贡献来确定总门电阻,特别地,其中每个电阻贡献基于电阻元件的电阻值,第一部分 从半导体鳍片进入电阻元件的电流和来自离开电阻元件的半导体鳍片的电流的第二部分。
    • 5. 发明授权
    • Method and apparatus for cooperative communications between groups of communication units
    • 通信单元组之间的协作通信的方法和装置
    • US08675482B1
    • 2014-03-18
    • US12536177
    • 2009-08-05
    • Ning LuMichael Mayor
    • Ning LuMichael Mayor
    • G08C15/00
    • H04B1/7115H04B7/10H04W56/0005H04W56/0075
    • Enhanced reception in a communication system is achieved by synchronously combining transmissions from a cluster of transmitting communication devices at a group of distant receiving communication devices. The transmitting communication devices coordinate their transmissions such that each device transmits the same signal on the same communication channel at different transmission times. As a consequence of the spatial diversity of the transmitting and receiving communication devices and the temporal diversity of the transmission times, the transmitted signals arrive at the receiving communication devices at different times. The receiving communication devices each essentially treat the different transmitted signals as though they were different multipath signals from a single transmitting communication device. This permits detection at a greater range or with a lower bit error rate. In addition, the many-to-many configuration enables a communication protocol to be maintained without modification of the protocol or termination (or interruption) of a protocol message sequence.
    • 在通信系统中的增强的接收是通过在一组远程接收通信设备上同步组合来自一组发射通信设备的传输来实现的。 发射通信设备协调其传输,使得每个设备在不同的传输时间在相同的通信信道上发送相同的信号。 作为发送和接收通信设备的空间分集和传输时间的时间分集的结果,所发送的信号在不同时间到达接收通信设备。 接收通信设备各自基本上将不同的发射信号视为就像它们是来自单个发射通信设备的不同的多径信号。 这允许在较大范围或较低位错误率下进行检测。 此外,多对多配置使得能够维护通信协议而不修改协议或协议消息序列的终止(或中断)。
    • 7. 发明申请
    • MODELING THE TOTAL PARASITIC RESISTANCES OF THE SOURCE/DRAIN REGIONS OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR
    • 建立多灰度场效应晶体管的源/漏区域的总共阻抗
    • US20130289964A1
    • 2013-10-31
    • US13455181
    • 2012-04-25
    • Ning Lu
    • Ning Lu
    • G06F17/50
    • G06F17/5036
    • In the embodiments, a full resistive network is used to determine resistance contributions to the total parasitic resistance of each source/drain region of a multi-fin multi-gate field effect transistor (MUGFET). These resistance contributions include: a first resistance contribution of end portions of the fins, which are connected in pseudo-parallel by a local interconnect; second resistance contributions of segments of the local interconnect, which are connected in pseudo-series; and any other resistance contributions of any other resistive elements between the end portions of the fins and a single resistive element through which all the diffusion region current flows. The multi-fin MUGFET is then represented in a netlist as a simple field effect transistor with the total parasitic resistances represented as single resistive elements connected to the source/drain nodes of that field effect transistor. This simplified netlist is then used to simulate performance of the multi-fin MUGFET.
    • 在实施例中,使用全电阻网络来确定对多鳍多栅极场效应晶体管(MUGFET)的每个源极/漏极区域的总寄生电阻的电阻贡献。 这些电阻贡献包括:翅片端部的第一电阻贡献,其通过局部互连以伪并联连接; 局部互连段的第二阻力贡献,以伪序列连接; 以及翅片端部之间的任何其它电阻元件和所有扩散区域电流通过的单一电阻元件的任何其它电阻贡献。 然后将多鳍MUGFET表示为网表,作为简单的场效应晶体管,其总寄生电阻表示为连接到该场效应晶体管的源极/漏极节点的单个电阻元件。 然后使用这个简化的网表来模拟多鳍MUGFET的性能。
    • 8. 发明申请
    • SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR STREAMING OUT OF DATA FOR VIDEO TRANSCODING AND OTHER APPLICATIONS
    • 用于流出数据的系统,方法和计算机程序产品,用于视频转码和其他应用
    • US20130170543A1
    • 2013-07-04
    • US13341444
    • 2011-12-30
    • Ning LuHong H. Jiang
    • Ning LuHong H. Jiang
    • H04N7/26H04N7/32
    • H04N19/40H04N19/142H04N19/46H04N19/70
    • Methods, systems, and computer program products that use descriptive information in a coded video stream to accelerate the transcoding process. This information, including information that is sometimes known as syntax information, may reside explicitly in headers of a coded stream. Examples of such information may include motion vectors, macroblock types, intra block prediction modes, inter block descriptive information, and quantization parameters. Other descriptive information may be derived from the actual coded macroblocks, e.g., the number of bits used to encode a macroblock, or the number of non-zero coefficients used in encoding, or the coefficients themselves. Such descriptive information may be used directly in the encoding phase of the transcoding process to improve the speed and throughput of the transcoding. Such descriptive information may also be used to enhance other video processing applications, such as scene change detection, determining object segmentation, or motion censoring.
    • 使用编码视频流中的描述信息来加速转码过程的方法,系统和计算机程序产品。 该信息(包括有时称为语法信息的信息)可以明确驻留在编码流的标题中。 这种信息的示例可以包括运动矢量,宏块类型,帧内块预测模式,块间描述信息和量化参数。 可以从实际的编码宏块(例如,用于对宏块进行编码的位数,或编码中使用的非零系数的数量)或系数本身导出其他描述信息。 这种描述性信息可以直接用于代码转换过程的编码阶段,以提高转码的速度和吞吐量。 这种描述性信息也可用于增强其他视频处理应用,例如场景变化检测,确定对象分割或运动审查。
    • 9. 发明授权
    • Method and system for constructing corner models for multiple performance targets
    • 构建多个性能目标的角模型的方法和系统
    • US08423341B2
    • 2013-04-16
    • US12581208
    • 2009-10-19
    • Ning Lu
    • Ning Lu
    • G06F17/50G06F7/60G06F17/10
    • G06F17/5036
    • A method, system and article of manufacture are disclosed for constructing corner models for multiple performance targets for circuit simulations. The method includes identifying N (N≧2) performance targets F1, F2, . . . , FN, and obtaining their correlation matrix R, calculating a normalized joint probability density (JPD); and building a common and optimal corner for the N targets. The method further includes constructing corner models to cover both lower and upper bounds of the performance targets; and determining an optimal common corner solution for each corner by maximizing a normalized JPD among all possible common corner solutions for that corner.
    • 公开了一种用于构建用于电路模拟的多个性能目标的角模型的方法,系统和制造。 该方法包括识别N(N≥2)性能目标F1,F2。 。 。 FN,并获得其相关矩阵R,计算归一化关节概率密度(JPD); 并为N个目标建立一个共同和最佳的角度。 该方法还包括构建拐角模型以覆盖性能目标的下限和上限; 并且通过使针对该角的所有可能的常见角解中的归一化的JPD最大化来确定每个角的最佳公共角解。
    • 10. 发明申请
    • METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE
    • 用于建模与绝缘体绝缘体器件的扩散区域相关的电容的方法,系统和程序存储装置
    • US20130007686A1
    • 2013-01-03
    • US13171528
    • 2011-06-29
    • Ning Lu
    • Ning Lu
    • G06F17/50
    • G06F17/5036G06F17/5081
    • Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (CD-S). This formula can have a perimeter component, including a side edge component and, if applicable, a corner component, both of which account for the fact that CD-S is generally dependent on the distances between the diffusion region and any adjacent conductive structures. Additionally, the parasitic capacitance between the diffusion region and any adjacent conductive structure (CD-D) can be determined based on such distances.
    • 公开了一种用于精确地建模与绝缘体上硅(SOI)器件的扩散区域相关联的寄生电容的方法,系统和程序存储设备的实施例,并且至少部分地基于邻近的绝缘体上硅 导电结构。 在这些实施例中,可以分析集成电路设计的布局以确定扩散区域的形状,尺寸和邻近信息。 然后,可以开发公式并用于确定扩散区域和下面的衬底(CD-S)之间的寄生电容。 该公式可以具有周边部件,包括侧边缘部件,以及(如果适用的话)拐角部件,这两个部件考虑到CD-S通常取决于扩散区域和任何相邻导电结构之间的距离的事实。 此外,可以基于这样的距离来确定扩散区域和任何相邻的导电结构(CD-D)之间的寄生电容。