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1. 发明申请

US20090267670A1 CIRCUIT WITH PARALLEL FUNCTIONAL CIRCUITS WITH MULTI-PHASE CONTROL INPUTS 有权
标题翻译：具有多相控制输入的并行功能电路的电路
公开(公告)号：US20090267670A1
公开(公告)日：2009-10-29
申请号：US12518696
申请日：2007-12-10
申请人： Paul Wielage , Martinus T. Bennebroek
发明人： Paul Wielage , Martinus T. Bennebroek
IPC分类号： H03K3/00 , G11C19/00
CPC分类号： G11C19/287 , G06F9/3869
摘要： A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset. Thus the pulse durations of the one shot circuits are adapted to the number of functional circuits to ensure sufficient signal development.
摘要翻译：电路具有多个功能电路（100a-f），每个具有多相控制输入。控制电路并联驱动每相的输入。控制电路（120a-c）包括一个单触发电路链（120a-c），每条链包括双稳电路（121）。链中的第一单触发电路的双稳态电路（121）具有耦合到基本控制信号输入（126）的设置输入，剩余或每个剩余单次触发的双稳态电路（121）链路中的电路（120a-c）具有其前身在链中的设定输入输出。每个双稳态电路（121）具有耦合到多相控制输出（14a-c）中的相应一个的输出和耦合到多相控制输出（14a-c）中的相应一个的复位输入。通过功能电路加载多相控制输出（14a-c）会导致复位延迟。因此，单触发电路的脉冲持续时间适应于功能电路的数量，以确保足够的信号发展。

2. 发明授权

US07839168B2 Circuit with parallel functional circuits with multi-phase control inputs 有权
标题翻译：具有多相控制输入并联功能电路的电路
公开(公告)号：US07839168B2
公开(公告)日：2010-11-23
申请号：US12518696
申请日：2007-12-10
申请人： Paul Wielage , Martinus T. Bennebroek
发明人： Paul Wielage , Martinus T. Bennebroek
IPC分类号： H03K19/173
CPC分类号： G11C19/287 , G06F9/3869
摘要： A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset. Thus the pulse durations of the one shot circuits are adapted to the number of functional circuits to ensure sufficient signal development.
摘要翻译：电路具有多个功能电路（100a-f），每个具有多相控制输入。控制电路并联驱动每相的输入。控制电路（120a-c）包括一个单触发电路链（120a-c），每条链包括双稳电路（121）。链中的第一单触发电路的双稳态电路（121）具有耦合到基本控制信号输入（126）的设置输入，剩余或每个剩余单次触发的双稳态电路（121）链路中的电路（120a-c）具有其前身在链中的设定输入输出。每个双稳态电路（121）具有耦合到多相控制输出（14a-c）中的相应一个的输出和耦合到多相控制输出（14a-c）中的相应一个的复位输入。通过功能电路加载多相控制输出（14a-c）会导致复位延迟。因此，单触发电路的脉冲持续时间适应于功能电路的数量，以确保足够的信号发展。

3. 发明授权

US06829736B1 Method of testing a memory 失效
标题翻译：测试内存的方法
公开(公告)号：US06829736B1
公开(公告)日：2004-12-07
申请号：US09831657
申请日：2001-05-11
申请人： Erik Jan Marinissen , Guillaume Elisabeth Andreas Lousberg , Paul Wielage
发明人： Erik Jan Marinissen , Guillaume Elisabeth Andreas Lousberg , Paul Wielage
IPC分类号： H03M1300
CPC分类号： G11C29/44
摘要： A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.
摘要翻译：内置自诊断（BISD）存储器件包括一个二维存储器阵列，其具有可由外部修复设备代替二维存储器阵列中的各种存储器行和列的冗余存储器行和列。刺激发生器在测试模式期间向存储器阵列输出多地址测试序列。响应评估器从内存接收响应。故障表存储响应的评估，并将其传达给外部维修设施。修复寄存器指示哪些内存列已被中间计划由响应评估程序进行修复。列计数器每个累加在相应存储器列中检测到的存储器位故障的数量。全部设置在单个集成电路半导体器件中。

4. 发明申请

US20070001727A1 Static latch 审中-公开
标题翻译：静态锁定
公开(公告)号：US20070001727A1
公开(公告)日：2007-01-04
申请号：US10570294
申请日：2004-08-26
申请人： Paul Wielage
发明人： Paul Wielage
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： A static latch (80) transfers input data (D) and its complement (DN) to an output terminal (100) and a complementary output terminal (98) when enabled and maintains the input data (D, DN) on the output terminals (100,98) when not enabled. The input data (D, DN) gate second and third transistors (86,88), the enable signal (G) gates a first transistor (90), such that when the latch (80) is enabled, the first and second transistors (98,86) and the first and third transistors (90,88) transfer the input data (D) and its complement (DN) to the specified output terminals (100,98) and when the latch (80) is disabled disconnects the input terminals (92,94) to maintain the current output values (Q,QN).
摘要翻译：当使能时，静态锁存器（80）将输入数据（D）及其补码（DN）传送到输出端子（100）和互补输出端子（98），并将输入数据（D，DN）保持在输出端子 100,98）未启用。输入数据（D，DN）门第二和第三晶体管（86,88），使能信号（G）门控第一晶体管（90），使得当锁存器（80）被使能时，第一和第二晶体管 98,86），并且第一和第三晶体管（90,88）将输入数据（D）及其补码（DN）传送到指定的输出端子（100,98），并且当锁存器（80）被禁用时，输入端子（92,94）以维持电流输出值（Q，QN）。

5. 发明申请

US20060077974A1 Return path derivation in packet-switched networks 审中-公开
标题翻译：分组交换网络中的返回路径导出
公开(公告)号：US20060077974A1
公开(公告)日：2006-04-13
申请号：US10539199
申请日：2003-11-18
申请人： Kees Goossens , Edwin Rijpkema , Paul Wielage
发明人： Kees Goossens , Edwin Rijpkema , Paul Wielage
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/36
摘要： A network for transporting data consists of a group of two or more nodes, such as switches, routers or computer systems, linked together. Data is transported from a source node to a destination node through the network. In packed-switched networks, small units of data called packets are routed through the network from a source node to a destination node. These packets can also be used to program the network. In some cases it is required that the packet travels the return path to the source node. In the present invention, the return path is derived from information stored in the nodes of the network.
摘要翻译：用于传输数据的网络由两个或更多个节点组成，例如交换机，路由器或计算机系统，链接在一起。数据通过网络从源节点传送到目的地节点。在打包交换网络中，称为数据包的小型数据单元通过网络从源节点路由到目标节点。这些数据包也可用于对网络进行编程。在某些情况下，要求数据包传播到源节点的返回路径。在本发明中，返回路径是从存储在网络节点中的信息导出的。

6. 发明授权

US07971038B2 Asynchronous ripple pipeline 失效
标题翻译：异步波纹管道
公开(公告)号：US07971038B2
公开(公告)日：2011-06-28
申请号：US12065636
申请日：2006-09-04
申请人： Paul Wielage
发明人： Paul Wielage
IPC分类号： G06F9/30
CPC分类号： G06F7/00 , G06F5/08 , G06F9/3871
摘要： An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).
摘要翻译：异步波纹管线具有多个级，每个级具有控制器（18）和寄存器（16）。控制器具有寄存器控制输出（21）和组合确认和请求输出（20）以及请求输入（22）和确认输入（24）。所使用的协议具有单个信号，在阶段（30）的组合确认和请求输出（20）上输出，其既作为对下一级（32）的请求又对先前级（34）的确认起作用。

7. 发明授权

US07562244B2 Method for data signal transfer across different clock-domains 有权
标题翻译：不同时钟域数据信号传输的方法
公开(公告)号：US07562244B2
公开(公告)日：2009-07-14
申请号：US10555747
申请日：2004-05-04
申请人： Paul Wielage
发明人： Paul Wielage
IPC分类号： G06F13/42 , G06F1/00 , G06F3/00 , G06F11/00
CPC分类号： H04L7/02
摘要： In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of said data signal is started before the synchronization of said data signal is completed in said current clock-domain.
摘要翻译：在用于跨不同时钟域的数据信号传输的方法中，包括数据信号与所述数据信号被处理的当前时钟域的同步，所述数据信号的处理在所述数据信号的同步完成之前开始表示当前时钟域。

8. 发明授权

US07185220B2 Information exchange between locally synchronous circuits 有权
标题翻译：本地同步电路之间的信息交换
公开(公告)号：US07185220B2
公开(公告)日：2007-02-27
申请号：US10500520
申请日：2002-12-06
申请人： Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters , Paul Wielage
发明人： Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters , Paul Wielage
IPC分类号： G06F1/04 , G06F5/06
CPC分类号： G06F1/08
摘要： A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.
摘要翻译：本地同步电路模块具有延迟电路，其具有耦合到时钟输入的输入和输出。延迟电路提供了延迟，当并入时钟振荡器中时，可以确保在存储元件之间传送信息所需的时钟周期至少等同于长度。提供握手电路，用于产生用于本地同步电路模块和另一电路之间的定时信息传送的握手信号。握手电路包括延迟电路，使得在握手事务期间的握手信号的至少一部分通过行进延迟电路来计时，并被施加到时钟输入以对本地同步电路模块进行时钟。

9. 发明申请

US20060274870A1 Method for data signal transfer across different clock-domains 有权
公开(公告)号：US20060274870A1
公开(公告)日：2006-12-07
申请号：US10555747
申请日：2004-05-04
申请人： Paul Wielage
发明人： Paul Wielage
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of said data signal is started before the synchronization of said data signal is completed in said current clock-domain.

10. 发明授权

US08952976B2 SIMD parallel processor architecture 有权
标题翻译： SIMD并行处理器架构
公开(公告)号：US08952976B2
公开(公告)日：2015-02-10
申请号：US13057491
申请日：2009-08-05
申请人： Alexander Alexandrovich Danilin , Richard Petrus Kleihorst , Paul Wielage
发明人： Alexander Alexandrovich Danilin , Richard Petrus Kleihorst , Paul Wielage
IPC分类号： G09G5/37 , G06F15/80 , G06F13/00 , G06F15/16 , G06T1/20
CPC分类号： G06F15/16 , G06T1/20
摘要： A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.
摘要翻译：描述了一种SIMD并行处理器，其包括包括处理元件，相关联的数据存储组件和被配置为使得能够访问与至少一个处理元件相关联的数据存储组件中的至少一个的阵列的阵列; 一个控制处理器; 存储器控制装置，被配置为能够对所述控制处理器的所述访问装置中的至少一个进行寻址; 以及连接装置，被配置为将存储器控制装置连接到存取装置。

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