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1. 发明授权

US07947591B2 Semiconductor devices with dual-metal gate structures and fabrication methods thereof 有权
标题翻译：具有双金属栅极结构的半导体器件及其制造方法
公开(公告)号：US07947591B2
公开(公告)日：2011-05-24
申请号：US12099827
申请日：2008-04-09
申请人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
发明人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
摘要翻译：具有双金属栅极结构的半导体器件及其制造方法。提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层插入层和第二金属层上的多晶硅层。第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

2. 发明申请

US20080188044A1 SEMICONDUCTOR DEVICES WITH DUAL-METAL GATE STRUCTURES AND FABRICATION METHODS THEREOF 有权
公开(公告)号：US20080188044A1
公开(公告)日：2008-08-07
申请号：US12099827
申请日：2008-04-09
申请人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
发明人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

3. 发明申请

US20080099851A1 SEMICONDUCTOR DEVICES WITH DUAL-METAL GATE STRUCTURES AND FABRICATION METHODS THEREOF 有权
标题翻译：具有双金属门结构的半导体器件及其制造方法
公开(公告)号：US20080099851A1
公开(公告)日：2008-05-01
申请号：US11552704
申请日：2006-10-25
申请人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
发明人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
摘要翻译：具有双金属栅极结构的半导体器件及其制造方法。提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层插入层和第二金属层上的多晶硅层。第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

4. 发明授权

US07378713B2 Semiconductor devices with dual-metal gate structures and fabrication methods thereof 有权
标题翻译：具有双金属栅极结构的半导体器件及其制造方法
公开(公告)号：US07378713B2
公开(公告)日：2008-05-27
申请号：US11552704
申请日：2006-10-25
申请人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
发明人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
IPC分类号： H01L27/092 , H01L29/423
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
摘要翻译：具有双金属栅极结构的半导体器件及其制造方法。提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层插入层和第二金属层上的多晶硅层。第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

5. 发明申请

US20070228480A1 CMOS device having PMOS and NMOS transistors with different gate structures 审中-公开
标题翻译：具有具有不同栅极结构的PMOS和NMOS晶体管的CMOS器件
公开(公告)号：US20070228480A1
公开(公告)日：2007-10-04
申请号：US11395175
申请日：2006-04-03
申请人： Fong-Yu Yen , Peng-Fu Hsu , Ying Jin
发明人： Fong-Yu Yen , Peng-Fu Hsu , Ying Jin
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A CMOS device has PMOS and NMOS transistors with different gate structures overlying a semiconductor device. A first gate structure overlying the PMOS device region has a first gate dielectric layer overlying the semiconductor substrate, and a first gate conductor overlying the first gate dielectric layer. A second gate device region overlying the NMOS device region has a second gate dielectric layer overlying the semiconductor substrate, and a second gate conductor overlying the first gate dielectric layer. The first gate conductor has a silicon-based material layer, and the second gate conductor has a metal-based material layer.
摘要翻译： CMOS器件具有覆盖半导体器件的不同栅极结构的PMOS和NMOS晶体管。覆盖PMOS器件区的第一栅极结构具有覆盖在半导体衬底上的第一栅极电介质层和覆盖第一栅极介电层的第一栅极导体。覆盖NMOS器件区域的第二栅极器件区域具有覆盖半导体衬底的第二栅极介电层和覆盖第一栅极介电层的第二栅极导体。第一栅极导体具有硅基材料层，第二栅极导体具有金属基材料层。

6. 发明申请

US20100303016A1 System and Method for Transport Block Size Design for Multiple-Input, Multiple-Output (MIMO) in a Wireless Communications System 有权
标题翻译：用于无线通信系统中多输入多输出（MIMO）的传输块大小设计的系统和方法
公开(公告)号：US20100303016A1
公开(公告)日：2010-12-02
申请号：US12791669
申请日：2010-06-01
申请人： Ying Jin , Yufei Blankenship
发明人： Ying Jin , Yufei Blankenship
IPC分类号： H04W40/00
CPC分类号： H04L27/0008
摘要： In one embodiment, a method for transmitting information includes processing a downlink transport channel to generate a transport block (TB) having a TB size. The TB size is selected by selecting a modulation and coding scheme index (ITBS) and a physical resource block index (NPRB). The TB size for the selected ITBS and NPRB is selected so that an effective code rate at an user equipment (UE) does not exceed a specified threshold. The effective code rate is defined as a number of downlink (DL) information bits including TB cyclic redundancy check (CRC) bits and code block CRC bits divided by a number of physical channel bits on Physical Downlink Shared Channel (PDSCH). The transport block is mapped to multiple spatial layers. The number of spatial layers N is greater than or equal to three. The multiple spatial layers are transmitted to the UE.
摘要翻译：在一个实施例中，一种用于发送信息的方法包括处理下行链路传输信道以生成具有TB大小的传输块（TB）。通过选择调制和编码方案索引（ITBS）和物理资源块索引（NPRB）来选择TB大小。所选择的ITBS和NPRB的TB大小被选择为使用户设备（UE）的有效码率不超过指定的阈值。有效码率被定义为包括TB循环冗余校验（CRC）比特和码块CRC比特除以物理下行链路共享信道（PDSCH）上的物理信道比特数的下行链路（DL）信息比特数。传输块被映射到多个空间层。空间层数N大于或等于3。多个空间层被传送到UE。

7. 发明授权

US08548027B2 Multi-ary error-correcting code transmitting and receiving apparatuse, data transmission system, and relevant method 有权
标题翻译：多方差纠错码发送接收机，数据传输系统及相关方法
公开(公告)号：US08548027B2
公开(公告)日：2013-10-01
申请号：US12771757
申请日：2010-04-30
申请人： Yanxing Zeng , Raymond W. K. Leung , Ying Jin , Chao Zhang
发明人： Yanxing Zeng , Raymond W. K. Leung , Ying Jin , Chao Zhang
IPC分类号： H04B1/00
CPC分类号： H04L1/004 , H03M13/134 , H03M13/27 , H03M13/2957 , H03M13/6325 , H04L1/005 , H04L1/0056 , H04L1/0071
摘要： The embodiments of the present invention disclose an apparatus for transmitting multi-ary error-correcting codes, an apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods to simplify operations. The apparatus for transmitting multi-ary error-correcting codes includes: a multi-ary channel encoder, adapted to perform multi-ary coding for source data frames of a user to obtain encoded sequences; a symbol mapper, adapted to perform symbol mapping for the encoded sequences to obtain symbol sequences; and a spreading and interleaving unit, adapted to spread and interleave the symbol sequences. Moreover, a corresponding apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods are provided.
摘要翻译：本发明的实施例公开了一种用于发送多重纠错码的装置，用于接收多重纠错码的装置，数据传输系统以及相关方法以简化操作。用于发送多重纠错码的装置包括：多进道信道编码器，适用于对用户的源数据帧执行多元编码以获得编码序列; 符号映射器，适于对编码序列执行符号映射以获得符号序列; 以及扩展和交织单元，适于扩展和交织符号序列。此外，提供了用于接收多重纠错码的相应装置，数据传输系统和相关方法。

8. 发明申请

US20110249590A1 System and Method for Multiplexing Control and Data Channels in a Multiple Input, Multiple Output Communications System 有权
标题翻译：多输入多输出通信系统中多路复用控制和数据通道的系统与方法
公开(公告)号：US20110249590A1
公开(公告)日：2011-10-13
申请号：US13153293
申请日：2011-06-03
申请人： Yufei Blankenship , Weimin Xiao , Ying Jin
发明人： Yufei Blankenship , Weimin Xiao , Ying Jin
IPC分类号： H04W72/00 , H04W24/00
CPC分类号： H04B7/0456 , H04B7/0632 , H04B7/0639 , H04L1/0003 , H04L1/0026 , H04L1/007 , H04L1/0073 , H04L1/1861 , H04L5/0023 , H04L5/0055 , H04L5/0057 , H04L5/006 , H04L27/2627 , H04W72/0413
摘要： A system and method for system and method for multiplexing control and data channels in a multiple input, multiple output (MIMO) communications system are provided. A method for transmitting control symbols and data symbols on multiple MIMO layers includes selecting a first set of codewords from Ncw codewords, distributing control symbols onto the first set of layers, placing data symbols of the first set of codewords onto the first set of layers, placing data symbols of the (Ncw-Ncw1) remaining codewords to remaining layers if Ncw>Ncw1, and transmitting the multiple MIMO layers. The first set of codewords is associated with a first set of layers from the multiple MIMO layers, and the Ncw codewords are to be transmitted simultaneously and the first set of codewords comprises Ncw1 MIMO codewords, where Ncw and Ncw1 are integers greater than or equal to 1. The remaining layers are MIMO layers from the multiple MIMO layers not in the first set of layers.
摘要翻译：提供了一种用于在多输入多输出（MIMO）通信系统中复用控制和数据信道的系统和方法的系统和方法。一种用于在多个MIMO层上发送控制符号和数据符号的方法包括从Ncw码字中选择第一组码字，将控制符号分配到第一组层上，将第一组码字的数据符号放置在第一组层上，如果Ncw> Ncw1，将（Ncw-Ncw1）剩余码字的数据符号放置到剩余层，并发送多个MIMO层。第一组码字与来自多个MIMO层的第一组层相关联，并且Ncw码字将被同时传输，并且第一组码字包括Ncw1个MIMO码字，其中Ncw和Ncw1是大于或等于其余层是来自多个MIMO层的MIMO层，而不是第一组层。

9. 发明申请

US20100239035A1 System and Method for Multiple Input, Multiple Output Layer Mapping 有权
标题翻译：多输入多输出层映射的系统和方法
公开(公告)号：US20100239035A1
公开(公告)日：2010-09-23
申请号：US12725203
申请日：2010-03-16
申请人： Yufei Blankenship , Ying Jin , Oghenekome Oteri
发明人： Yufei Blankenship , Ying Jin , Oghenekome Oteri
IPC分类号： H04L27/28
CPC分类号： H04L1/0656
摘要： A system and method for multiple input, multiple output (MIMO) uplink (UL) layer mapping is provided. A method for mapping modulation symbols to multiple input, multiple output (MIMO) layers includes receiving a first set of modulation symbols corresponding to a first transport block, partitioning the first set of modulation symbols into M1 parts, assigning each of the M1 parts to one of the M1 MIMO layers, and transmitting the modulation symbols mapped onto the M1 MIMO layers. The first transport block includes a plurality of code blocks, all modulation symbols of at least one code block belongs to a single part, and M1 is a positive integer value greater than one.
摘要翻译：提供了一种用于多输入多输出（MIMO）上行链路（UL）层映射的系统和方法。将调制符号映射到多输入多输出（MIMO）层的方法包括：接收对应于第一传输块的第一组调制符号，将第一组调制符号划分为M1部分，将M1部分分配给一个并且发送映射到M1 MIMO层上的调制符号。第一传输块包括多个码块，至少一个码块的所有调制符号属于单个部分，并且M1是大于1的正整数值。

10. 发明申请

US20100220768A1 MULTI-ARY ERROR-CORRECTING CODE TRANSMITTING AND RECEIVING APPARATUSE, DATA TRANSMISSION SYSTEM, AND RELEVANT METHOD 有权
标题翻译：多重错误修改代码发送和接收设备，数据传输系统和相关方法
公开(公告)号：US20100220768A1
公开(公告)日：2010-09-02
申请号：US12771757
申请日：2010-04-30
申请人： Yanxing Zeng , Raymond W.K. Leung , Ying Jin , Chao Zhang
发明人： Yanxing Zeng , Raymond W.K. Leung , Ying Jin , Chao Zhang
IPC分类号： H04B1/69 , H04B1/04 , H04B1/16
CPC分类号： H04L1/004 , H03M13/134 , H03M13/27 , H03M13/2957 , H03M13/6325 , H04L1/005 , H04L1/0056 , H04L1/0071
摘要： The embodiments of the present invention disclose an apparatus for transmitting multi-ary error-correcting codes, an apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods to simplify operations. The apparatus for transmitting multi-ary error-correcting codes includes: a multi-ary channel encoder, adapted to perform multi-ary coding for source data frames of a user to obtain encoded sequences; a symbol mapper, adapted to perform symbol mapping for the encoded sequences to obtain symbol sequences; and a spreading and interleaving unit, adapted to spread and interleave the symbol sequences. Moreover, a corresponding apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods are provided.
摘要翻译：本发明的实施例公开了一种用于发送多重纠错码的装置，用于接收多重纠错码的装置，数据传输系统以及相关方法以简化操作。用于发送多重纠错码的装置包括：多进道信道编码器，适用于对用户的源数据帧执行多元编码以获得编码序列; 符号映射器，适于对编码序列执行符号映射以获得符号序列; 以及扩展和交织单元，适于扩展和交织符号序列。此外，提供了用于接收多重纠错码的相应装置，数据传输系统和相关方法。

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