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1. 发明授权

US07941637B2 Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions 有权
标题翻译：串联耦合的处理器核心组传播存储器写入包，同时保持每个组内的一致性，转向耦合到存储器分区的交换机
公开(公告)号：US07941637B2
公开(公告)日：2011-05-10
申请号：US12103250
申请日：2008-04-15
申请人： Perry H. Pelley, III , George P. Hoekstra , Lucio F. C. Pessoa
发明人： Perry H. Pelley, III , George P. Hoekstra , Lucio F. C. Pessoa
IPC分类号： G06F15/80
CPC分类号： G06F15/16
摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
摘要翻译：系统在第一相干组中具有第一多个核心。每个核心以数据包传输数据。核心直接串联耦合以形成串行路径。数据包沿串行路径传输。串行路径在一端耦合到分组交换机。分组交换机耦合到存储器。第一多个核心和分组交换机在集成电路上。存储器可能集成在或不在集成电路上。在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

2. 发明授权

US07564738B2 Double-rate memory 有权
标题翻译：双速率内存
公开(公告)号：US07564738B2
公开(公告)日：2009-07-21
申请号：US11464129
申请日：2006-08-11
申请人： Perry H. Pelley, III , George P. Hoekstra
发明人： Perry H. Pelley, III , George P. Hoekstra
IPC分类号： G11C8/16
CPC分类号： G11C8/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18
摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.
摘要翻译：双速率存储器具有以行和列排列的单个字线存储单元阵列。单个字线存储单元通过第一端口提供和存储数据。寻址和控制电路耦合到单个字线存储单元的阵列。寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。

3. 发明授权

US4802129A RAM with dual precharge circuit and write recovery circuitry 失效
标题翻译： RAM具有双预充电电路和写恢复电路
公开(公告)号：US4802129A
公开(公告)日：1989-01-31
申请号：US128559
申请日：1987-12-03
申请人： George P. Hoekstra , Perry H. Pelley, III
发明人： George P. Hoekstra , Perry H. Pelley, III
IPC分类号： G11C7/10 , G11C7/22 , G11C11/419 , G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C7/10 , G11C7/22
摘要： A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled during the presence of a write enable pulse. The write enable pulse is generated in response to a read mode to write mode transition and also in response to a transition of the data input signal. The data lines are precharged in response to a transition of the data input signal that occurs during the write mode.
摘要翻译：通过由写入驱动器驱动的数据线写入存储器。数据线被耦合到由列地址确定的所选位线对。数据线由写入驱动器驱动到代表数据输入信号的逻辑状态。在存在写使能脉冲时，写驱动器被使能。写使能脉冲响应于写模式转换的读模式并且还响应于数据输入信号的转换而被产生。响应于在写入模式期间发生的数据输入信号的转变，数据线被预充电。

4. 发明授权

US08090913B2 Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory 有权
标题翻译：串行耦合处理核心的一致性组将包含写入包的一致性信息传播到存储器
公开(公告)号：US08090913B2
公开(公告)日：2012-01-03
申请号：US12972878
申请日：2010-12-20
申请人： Perry H. Pelley, III , George P. Hoekstra , Lucio F. Pessoa
发明人： Perry H. Pelley, III , George P. Hoekstra , Lucio F. Pessoa
IPC分类号： G06F12/08
CPC分类号： G06F15/16
摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
摘要翻译：系统在第一相干组中具有第一多个核心。每个核心以数据包传输数据。核心直接串联耦合以形成串行路径。数据包沿串行路径传输。串行路径在一端耦合到分组交换机。分组交换机耦合到存储器。第一多个核心和分组交换机在集成电路上。存储器可能集成在或不在集成电路上。在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

5. 发明申请

US20100208537A1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) REFRESH 有权
标题翻译：动态随机存取存储器（DRAM）刷新
公开(公告)号：US20100208537A1
公开(公告)日：2010-08-19
申请号：US12388922
申请日：2009-02-19
申请人： Perry H. Pelley, III , George P. Hoekstra
发明人： Perry H. Pelley, III , George P. Hoekstra
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40622 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50016 , G11C2029/0407 , G11C2211/4061
摘要： A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.
摘要翻译：一种用于刷新动态随机存取存储器（DRAM）的方法包括以第一刷新率在DRAM的至少一部分上执行刷新，并以第二刷新率在DRAM的第二部分上执行刷新。第二部分包括在第一刷新率下不满足数据保留标准的一行或多行DRAM，并且第二刷新率大于第一刷新率。

6. 发明申请

US20100107037A1 MEMORY SYSTEM WITH ERROR CORRECTION AND METHOD OF OPERATION 有权
标题翻译：具有错误校正的记忆系统和操作方法
公开(公告)号：US20100107037A1
公开(公告)日：2010-04-29
申请号：US12260727
申请日：2008-10-29
申请人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
发明人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064
摘要： A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.
摘要翻译：提供了一种用于存储器的纠错的方法。该方法包括：提供第一存储器和第二存储器; 启动第一存储器的读取操作以检索数据; 对所述数据执行纠错码（ECC）处理，其中所述ECC处理用于确定所述数据的至少一部分是错误的并且用于提供校正数据; 并且确定所述错误数据的地址是否存储在所述第二存储器中，如果所述错误数据的地址被存储在所述第二存储器中，则将所述校正数据存储在所述第二存储器中，并且所述错误数据的地址未被存储在第二存储器中，将地址存储在第二存储器中。

7. 发明授权

US08402327B2 Memory system with error correction and method of operation 有权
标题翻译：具有纠错和操作方法的存储系统
公开(公告)号：US08402327B2
公开(公告)日：2013-03-19
申请号：US12260727
申请日：2008-10-29
申请人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
发明人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.
摘要翻译：提供了一种用于存储器的纠错的方法。该方法包括：提供第一存储器和第二存储器; 启动第一存储器的读取操作以检索数据; 对所述数据执行纠错码（ECC）处理，其中所述ECC处理用于确定所述数据的至少一部分是错误的并且用于提供校正数据; 并且确定所述错误数据的地址是否存储在所述第二存储器中，如果所述错误数据的地址被存储在所述第二存储器中，则将所述校正数据存储在所述第二存储器中，并且所述错误数据的地址未被存储在第二存储器中，将地址存储在第二存储器中。

8. 发明授权

US08400859B2 Dynamic random access memory (DRAM) refresh 有权
标题翻译：动态随机存取存储器（DRAM）刷新
公开(公告)号：US08400859B2
公开(公告)日：2013-03-19
申请号：US13169596
申请日：2011-06-27
申请人： Perry H. Pelley, III , George P. Hoekstra
发明人： Perry H. Pelley, III , George P. Hoekstra
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40622 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50016 , G11C2029/0407 , G11C2211/4061
摘要： A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.
摘要翻译：一种用于刷新动态随机存取存储器（DRAM）的方法包括以第一刷新率在DRAM的至少一部分上执行刷新，并以第二刷新率在DRAM的第二部分上执行刷新。第二部分包括在第一刷新率下不满足数据保留标准的一行或多行DRAM，并且第二刷新率大于第一刷新率。

9. 发明授权

US07990795B2 Dynamic random access memory (DRAM) refresh 有权
标题翻译：动态随机存取存储器（DRAM）刷新
公开(公告)号：US07990795B2
公开(公告)日：2011-08-02
申请号：US12388922
申请日：2009-02-19
申请人： Perry H. Pelley, III , George P. Hoekstra
发明人： Perry H. Pelley, III , George P. Hoekstra
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40622 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50016 , G11C2029/0407 , G11C2211/4061
摘要： A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.
摘要翻译：一种用于刷新动态随机存取存储器（DRAM）的方法包括以第一刷新率在DRAM的至少一部分上执行刷新，并且以第二刷新率在DRAM的第二部分上执行刷新。第二部分包括在第一刷新率下不满足数据保留标准的一行或多行DRAM，并且第二刷新率大于第一刷新率。

10. 发明申请

US20090259825A1 MULTI-CORE PROCESSING SYSTEM 有权
标题翻译：多核处理系统
公开(公告)号：US20090259825A1
公开(公告)日：2009-10-15
申请号：US12103250
申请日：2008-04-15
申请人： Perry H. Pelley, III , George P. Hoekstra , Lucio F.C. Pessoa
发明人： Perry H. Pelley, III , George P. Hoekstra , Lucio F.C. Pessoa
IPC分类号： G06F15/80
CPC分类号： G06F15/16
摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
摘要翻译：系统在第一相干组中具有第一多个核心。每个核心以数据包传输数据。核心直接串联耦合以形成串行路径。数据包沿串行路径传输。串行路径在一端耦合到分组交换机。分组交换机耦合到存储器。第一多个核心和分组交换机在集成电路上。存储器可能集成在或不在集成电路上。在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

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