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1. 发明授权

US08352685B2 Combining write buffer with dynamically adjustable flush metrics 有权
标题翻译：将写入缓冲区与动态可调整的flush指标相结合
公开(公告)号：US08352685B2
公开(公告)日：2013-01-08
申请号：US12860505
申请日：2010-08-20
申请人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
发明人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0891 , G06F12/0804
摘要： In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.
摘要翻译：在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为折叠。折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

2. 发明申请

US20120047332A1 Combining Write Buffer with Dynamically Adjustable Flush Metrics 有权
标题翻译：将写入缓冲区与动态调整冲洗指标相结合
公开(公告)号：US20120047332A1
公开(公告)日：2012-02-23
申请号：US12860505
申请日：2010-08-20
申请人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
发明人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
IPC分类号： G06F12/08 , G06F3/00 , G06F12/00
CPC分类号： G06F12/0891 , G06F12/0804
摘要： In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.
摘要翻译：在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。折叠的写入缓冲器条目及其中的折叠的写入操作可以包括至少一个写入操作，该写入操作已覆盖由以前的写入操作在缓冲区条目中。在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

3. 发明授权

US08555040B2 Indirect branch target predictor that prevents speculation if mispredict is expected 有权
标题翻译：间接分支目标预测器，如果预期有误预测，则可以防止投机
公开(公告)号：US08555040B2
公开(公告)日：2013-10-08
申请号：US12785939
申请日：2010-05-24
申请人： Andrew J. Beaumont-Smith , Ramesh Gunna
发明人： Andrew J. Beaumont-Smith , Ramesh Gunna
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3848
摘要： In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch.
摘要翻译：在一个实施例中，处理器实现间接分支目标预测器来预测间接分支指令的目标地址。间接分支目标预测器可以存储在先前执行间接分支期间生成的目标地址，并且可以使用存储的目标地址作为当前间接分支的预测。间接分支目标预测器还可以存储对应于每个存储的目标地址的验证标签。可以将验证标签与对应于正在预测的当前间接分支的类似数据进行比较。如果验证标签不匹配，则假定间接分支被错误预测（因为分支目标地址实际上属于不同的指令）。间接分支目标预测器可能会在误预测的间接分支之后抑制推测性执行，直到重新发送给错误的间接分支。

4. 发明申请

US20110289300A1 Indirect Branch Target Predictor that Prevents Speculation if Mispredict Is Expected 有权
标题翻译：间接分支目标预测器，如果预期出现预测，则可以防止投机
公开(公告)号：US20110289300A1
公开(公告)日：2011-11-24
申请号：US12785939
申请日：2010-05-24
申请人： Andrew J. Beaumont-Smith , Ramesh Gunna
发明人： Andrew J. Beaumont-Smith , Ramesh Gunna
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3848
摘要： In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch.
摘要翻译：在一个实施例中，处理器实现间接分支目标预测器来预测间接分支指令的目标地址。间接分支目标预测器可以存储在先前执行间接分支期间生成的目标地址，并且可以使用存储的目标地址作为当前间接分支的预测。间接分支目标预测器还可以存储对应于每个存储的目标地址的验证标签。可以将验证标签与对应于正在预测的当前间接分支的类似数据进行比较。如果验证标签不匹配，则假定间接分支被错误预测（因为分支目标地址实际上属于不同的指令）。间接分支目标预测器可能会在误预测的间接分支之后抑制推测性执行，直到重新发送给错误的间接分支。

5. 发明申请

US20120290818A1 Split Scheduler 有权
标题翻译：拆分计划程序
公开(公告)号：US20120290818A1
公开(公告)日：2012-11-15
申请号：US13557725
申请日：2012-07-25
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

6. 发明授权

US08364936B2 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies 有权
标题翻译：采用分割调度器的处理器，跟踪跟随其他操作相关性的低延迟操作相关性
公开(公告)号：US08364936B2
公开(公告)日：2013-01-29
申请号：US13557725
申请日：2012-07-25
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

7. 发明申请

US20130138931A1 MAINTAINING THE INTEGRITY OF AN EXECUTION RETURN ADDRESS STACK 有权
标题翻译：维护执行返回地址堆栈的完整性
公开(公告)号：US20130138931A1
公开(公告)日：2013-05-30
申请号：US13304885
申请日：2011-11-28
申请人： Ramesh B. Gunna , Peter J. Bannon , Andrew J. Beaumont-Smith
发明人： Ramesh B. Gunna , Peter J. Bannon , Andrew J. Beaumont-Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3855 , G06F9/3861
摘要： A processor and method for maintaining the integrity of an execution return address stack (RAS). The execution RAS is maintained in an accurate state by storing information regarding branch instructions in a branch information table. The first time a branch instruction is executed, an entry is allocated and populated in the table. If the branch instruction is re-executed, a pointer address is retrieved from the corresponding table entry and the execution RAS pointer is repositioned to the retrieved pointer address. The execution RAS can also be used to restore a speculative RAS due to a mis-speculation.
摘要翻译：一种用于维护执行返回地址堆栈（RAS）的完整性的处理器和方法。通过在分支信息表中存储有关分支指令的信息，将执行RAS维持在准确的状态。第一次执行分支指令时，会在表中分配并填充一个条目。如果分支指令被重新执行，则从对应的表条目检索指针地址，并且将执行RAS指针重新定位到检索的指针地址。执行RAS也可以用于恢复由于错误猜测而导致的投机RAS。

8. 发明授权

US08255671B2 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies 有权
标题翻译：采用分割调度器的处理器，跟踪跟随其他操作相关性的低延迟操作相关性
公开(公告)号：US08255671B2
公开(公告)日：2012-08-28
申请号：US12338769
申请日：2008-12-18
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

9. 发明授权

US09354886B2 Maintaining the integrity of an execution return address stack 有权
标题翻译：维护执行返回地址堆栈的完整性
公开(公告)号：US09354886B2
公开(公告)日：2016-05-31
申请号：US13304885
申请日：2011-11-28
申请人： Ramesh B. Gunna , Peter J. Bannon , Andrew J. Beaumont-Smith
发明人： Ramesh B. Gunna , Peter J. Bannon , Andrew J. Beaumont-Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3855 , G06F9/3861
摘要： A processor and method for maintaining the integrity of an execution return address stack (RAS). The execution RAS is maintained in an accurate state by storing information regarding branch instructions in a branch information table. The first time a branch instruction is executed, an entry is allocated and populated in the table. If the branch instruction is re-executed, a pointer address is retrieved from the corresponding table entry and the execution RAS pointer is repositioned to the retrieved pointer address. The execution RAS can also be used to restore a speculative RAS due to a mis-speculation.
摘要翻译：一种用于维护执行返回地址堆栈（RAS）的完整性的处理器和方法。通过在分支信息表中存储有关分支指令的信息，将执行RAS维持在准确的状态。第一次执行分支指令时，会在表中分配并填充一个条目。如果分支指令被重新执行，则从对应的表条目检索指针地址，并且将执行RAS指针重新定位到检索的指针地址。执行RAS也可以用于恢复由于错误猜测而导致的投机RAS。

10. 发明授权

US09009451B2 Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle 有权
标题翻译：指令类型问题通过调整发行周期的计数器增量量和未发布周期的减量量来达到阈值
公开(公告)号：US09009451B2
公开(公告)日：2015-04-14
申请号：US13285361
申请日：2011-10-31
申请人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
发明人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
IPC分类号： G06F9/30 , G06F1/32 , G06F9/38 , G06F11/30
CPC分类号： G06F9/3836 , G06F1/3206 , G06F1/329 , G06F9/3838 , G06F9/384 , G06F9/3869 , G06F11/30 , G06F11/3024 , G06F11/3062 , G06F2201/81 , G06F2201/88 , H01L2924/0002 , Y02D10/24 , H01L2924/00
摘要： A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.
摘要翻译：一种通过发布限制所选问题指令来降低功耗的系统和方法。处理器内的功率节流单元维持相关指令类型的指令发出计数。指令类型可以是由处理器内的执行核执行的支持的指令类型的子集。可以基于用于处理这些类型的指令的高功耗估计来选择指令类型。功率节流单元可以确定给定的指令发出次数超过给定的阈值。作为响应，功率节流单元可以选择给定的指令类型以限制相应的发行率。功率节流单元可以选择所选择的给定指令类型中的每一个的发布率，并将相关的发行率限制为所选择的发行率。给定的指令类型和相关的发行率限制的选择是可编程的。

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