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1. 发明授权

US08698812B2 Video display mode control 有权
标题翻译：视频显示模式控制
公开(公告)号：US08698812B2
公开(公告)日：2014-04-15
申请号：US11833533
申请日：2007-08-03
申请人： Edward G. Callway , David Glen , Andrew Gruber , Gaurav Arora , Philip Swan
发明人： Edward G. Callway , David Glen , Andrew Gruber , Gaurav Arora , Philip Swan
IPC分类号： G06F15/00
CPC分类号： H04N5/46 , H04N5/14 , H04N21/42607 , H04N21/42653 , H04N21/44008
摘要： A video graphics chip includes a graphics module configured to process incoming video information in accordance with different modes to produce a video output signal and to transmit the video output signal toward a display screen for rendering of video corresponding to the video information, and a display mode module coupled to the graphics module configured to analyze the incoming video information to determine a type of video associated with the incoming video information and to send a video mode indication of a preferred video processing mode for the incoming video information to the graphics module, where the graphics module is configured to process the incoming video information in accordance with a selected mode from the plurality of different modes based on the video mode indication received from the display module.
摘要翻译：视频图形芯片包括：图形模块，被配置为根据不同的模式处理输入的视频信息以产生视频输出信号，并将视频输出信号发送到用于呈现与视频信息相对应的视频的显示屏幕;以及显示模式模块，被配置为分析输入视频信息以确定与输入视频信息相关联的视频的类型，并且将用于输入视频信息的优选视频处理模式的视频模式指示发送到图形模块，其中，图形模块被配置为基于从显示模块接收的视频模式指示，根据来自多个不同模式的选择模式处理输入视频信息。

2. 发明授权

US07633549B2 Apparatus and method for image rendering 有权
标题翻译：图像渲染的装置和方法
公开(公告)号：US07633549B2
公开(公告)日：2009-12-15
申请号：US10837991
申请日：2004-05-03
申请人： Philip Swan
发明人： Philip Swan
IPC分类号： H04N11/20
CPC分类号： H04N7/0137 , H04N7/012 , H04N19/112
摘要： An apparatus and method for image rendering includes a first buffer operative to receive first video data. A motion mad updater receives video data from the first buffer and updates a motion map using the first video data. A grain information generator is coupled to the first buffer and receives the first video data to generate slope information based on the first video data. A grain information filter receives the slope information and filters the slope information to generate filtered slope information. A spatially interpolated field generator receives the filtered slope information and generates a spatially interpolated field. A maximum difference value generator generates a maximum difference value based on the update motion map. A base value generator receives the first video data and the spatially interpolated field and generates a base value therefrom. A missing video data generator generates missing first video data.
摘要翻译：一种用于图像渲染的装置和方法包括可操作以接收第一视频数据的第一缓冲器。运动疯狂更新器从第一缓冲器接收视频数据，并使用第一视频数据更新运动图。谷物信息发生器耦合到第一缓冲器并且接收第一视频数据以基于第一视频数据生成斜率信息。谷物信息滤波器接收斜率信息并对斜率信息进行滤波以产生滤波斜率信息。空间内插场产生器接收经滤波的斜率信息并产生空间内插场。最大差值发生器基于更新运动图生成最大差值。基值生成器接收第一视频数据和空间内插字段，并从其生成基值。丢失的视频数据生成器生成缺少的第一个视频数据。

3. 发明申请

US20080001972A1 METHOD AND APPARATUS FOR INDEPENDENT VIDEO AND GRAPHICS SCALING IN A VIDEO GRAPHICS SYSTEM 审中-公开
标题翻译：在视频图形系统中独立视频和图形缩放的方法和装置
公开(公告)号：US20080001972A1
公开(公告)日：2008-01-03
申请号：US11855676
申请日：2007-09-14
申请人： Edward Callway , Allen Porter , Chun-Chin Yeh , Philip Swan
发明人： Edward Callway , Allen Porter , Chun-Chin Yeh , Philip Swan
IPC分类号： G09G5/00
CPC分类号： G09G5/397 , G09G2320/0247 , G09G2340/0407 , G09G2340/125 , G09G2370/042
摘要： A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.
摘要翻译：通过接收视频数据流来实现视频图形系统中的独立视频和图形缩放的方法和装置，其中视频数据流包括第一格式的视频数据。还接收图形数据流，并且图形数据流包括第二格式的图形数据。基于第一格式和所选视频格式之间的比率来缩放视频数据流的视频数据，以产生缩放的视频流。类似地，图形数据流的图形数据基于第二格式和所选图形格式之间的比例进行缩放，以便产生缩放的图形流。缩放的视频流和缩放的图形流然后被合并以产生视频图形输出流。

4. 发明申请

US20070018482A1 FAIRING PANEL RETAINER APPARATUS 有权
标题翻译：公平面板保持器设备
公开(公告)号：US20070018482A1
公开(公告)日：2007-01-25
申请号：US11168292
申请日：2005-06-29
申请人： Clyde Tuohimaa , Philip Swan , Tim Hian , Neil Doherty
发明人： Clyde Tuohimaa , Philip Swan , Tim Hian , Neil Doherty
IPC分类号： B62D35/00
CPC分类号： B62D35/00 , B62D33/04
摘要： A fairing panel retainer can include a retainer strip that is configured to conform to the contour of a vehicle body. The retainer strip includes alternating body attachment segments and raised panel attachment segments in a generally corrugated configuration. In addition, each of the body attachment segments includes a body fastener interface configured to accept a permanent fixed fastener to attach the fairing panel retainer to the vehicle body. Each of the panel attachment segments can include a panel fastener interface, for example, a bore through the panel attachment segment and a fastener plate slidably attached to a lower surface of the panel attachment segment. The body fastener interfaces and the panel fastener interfaces can be closely aligned along a longitudinal line or arc of the retainer strip. The fairing panel retainer can also include a transition surface to provide a smooth transition from the vehicle body surface to a fairing panel.
摘要翻译：整流罩保持器可以包括构造成符合车体轮廓的保持器条。保持条包括交替的主体连接部分和凸起的面板连接部分，呈大致波纹状。另外，每个主体附接段包括主体紧固件接口，该主体紧固件接口被配置为接收永久固定紧固件以将整流罩保持器附接到车体。每个面板附接段可以包括面板紧固件接口，例如通过面板附接区段的孔和可滑动地附接到面板附接区段的下表面的紧固件板。主体紧固件接口和面板紧固件接口可以沿着保持器条的纵向线或弧线紧密对准。整流罩板固定器还可以包括过渡表面以提供从车身表面到整流罩的平滑过渡。

5. 发明申请

US20080088635A1 Video Display Mode Control 有权
标题翻译：视频显示模式控制
公开(公告)号：US20080088635A1
公开(公告)日：2008-04-17
申请号：US11833533
申请日：2007-08-03
申请人： Edward Callway , David Glen , Andrew Gruber , Gaurav Arora , Philip Swan
发明人： Edward Callway , David Glen , Andrew Gruber , Gaurav Arora , Philip Swan
IPC分类号： G06T1/00
CPC分类号： H04N5/46 , H04N5/14 , H04N21/42607 , H04N21/42653 , H04N21/44008
摘要： A video graphics chip includes a graphics module configured to process incoming video information in accordance with different modes to produce a video output signal and to transmit the video output signal toward a display screen for rendering of video corresponding to the video information, and a display mode module coupled to the graphics module configured to analyze the incoming video information to determine a type of video associated with the incoming video information and to send a video mode indication of a preferred video processing mode for the incoming video information to the graphics module, where the graphics module is configured to process the incoming video information in accordance with a selected mode from the plurality of different modes based on the video mode indication received from the display module.
摘要翻译：视频图形芯片包括：图形模块，被配置为根据不同的模式处理输入的视频信息以产生视频输出信号，并将视频输出信号发送到用于呈现与视频信息相对应的视频的显示屏幕;以及显示模式模块，被配置为分析输入视频信息以确定与输入视频信息相关联的视频的类型，并且将用于输入视频信息的优选视频处理模式的视频模式指示发送到图形模块，其中，图形模块被配置为基于从显示模块接收的视频模式指示，根据来自多个不同模式的选择模式处理输入视频信息。

6. 发明申请

US20050078214A1 Method and de-interlacing apparatus that employs recursively generated motion history maps 失效
标题翻译：采用递归生成运动历史图的方法和去隔行扫描仪
公开(公告)号：US20050078214A1
公开(公告)日：2005-04-14
申请号：US10661181
申请日：2003-09-11
申请人： Daniel Wong , Philip Swan , Daniel Doswald
发明人： Daniel Wong , Philip Swan , Daniel Doswald
IPC分类号： H04N5/14 , H04N5/44 , H04N7/01
CPC分类号： H04N7/012 , H04N5/144 , H04N7/0137 , H04N7/014
摘要： A de-interlacer includes recursive motion history map generating circuitry operative to determine a motion value associated with one or more pixels in interlaced fields based on pixel intensity information from at least two neighboring same polarity fields. The recursive motion history map generating circuitry generates a motion history map containing recursively generated motion history values for use in de-interlacing interlaced fields wherein the recursively generated motion history values are based, at least in part, on a decay function.
摘要翻译：解交织器包括递归运动历史图生成电路，用于基于来自至少两个相邻的相邻极性场的像素强度信息来确定与隔行场中的一个或多个像素相关联的运动值。递归运动历史图生成电路产生运动历史图，该运动历史图包含递归生成的运动历史值，用于去隔行隔行扫描场，其中递归生成的运动历史值至少部分地基于衰减函数。

7. 发明授权

US06788309B1 Method and apparatus for generating a video overlay 失效
标题翻译：用于生成视频叠加的方法和装置
公开(公告)号：US06788309B1
公开(公告)日：2004-09-07
申请号：US09678362
申请日：2000-10-03
申请人： Philip Swan , John Haberfellner
发明人： Philip Swan , John Haberfellner
IPC分类号： G09G500
CPC分类号： G06T1/20
摘要： A method and apparatus utilizes a display engine scaler to access source image that is located in memory, such as a frame buffer and also controls a second scaler, such as a front end scaler of a 2D/3D engine, which also accesses the frame buffer and is capable of scaling from a frame buffer memory and storing the scaled image back to the frame buffer.
摘要翻译：一种方法和装置利用显示引擎缩放器来访问位于诸如帧缓冲器的存储器中的源图像，并且还控制还访问帧缓冲器的第二缩放器，诸如2D / 3D引擎的前端缩放器并且能够从帧缓冲存储器缩放并将缩放的图像存储回帧缓冲器。

8. 发明授权

US06559859B1 Method and apparatus for providing video signals 有权
标题翻译：用于提供视频信号的方法和装置
公开(公告)号：US06559859B1
公开(公告)日：2003-05-06
申请号：US09339886
申请日：1999-06-25
申请人： William T. Henry , Philip Swan
发明人： William T. Henry , Philip Swan
IPC分类号： G09G502
CPC分类号： G09G5/006 , G09G5/395 , G09G2310/0235
摘要： A video graphics adapter is configured to provide both parallel and sequential color components to separate display monitors. When in a first state, the video graphics adapter provides individual color components to a video-output independent of each other color component, such that an entire frame of a red component will be provided to a video-out port for prior to, or subsequently after, an entire frame of the green component being provided to the video-out port. Each color component is provided to a common port. In response to a second configuration state, a traditional parallel red, green, blue (RGB) data port will be generated in order to provide data to a display device. In yet another configuration state, both the individual color components are provided at a common port, and the individual color components are provided in parallel to an RGB port.
摘要翻译：视频图形适配器被配置为提供并行和顺序颜色分量以分离显示器。当处于第一状态时，视频图形适配器将独立的颜色分量提供给独立于每个其它颜色分量的视频输出，使得红色分量的整个帧将被提供给视频输出端口用于在之前或之后之后，将绿色部件的整个框架提供给视频输出端口。每个颜色组件都提供给一个公共端口。响应于第二配置状态，将生成传统的并行红，绿，蓝（RGB）数据端口，以向显示设备提供数据。在另一种配置状态下，各个颜色分量都设置在公共端口处，并且各个颜色分量被平行于RGB端口提供。

9. 发明申请

US20120223938A1 METHOD AND SYSTEM FOR PROVIDING USER CONTROL OF TWO-DIMENSIONAL IMAGE DEPTH WITHIN THREE-DIMENSIONAL DISPLAY SPACE 审中-公开
标题翻译：在三维显示空间中提供用户控制二维图像深度的方法和系统
公开(公告)号：US20120223938A1
公开(公告)日：2012-09-06
申请号：US13040987
申请日：2011-03-04
申请人： Gabor Sines , Pavel Siniavine , Jitesh Arora , Alexander Zorin , Xingping Cao , Philip Swan
发明人： Gabor Sines , Pavel Siniavine , Jitesh Arora , Alexander Zorin , Xingping Cao , Philip Swan
IPC分类号： G06T15/00
CPC分类号： G06T19/00 , G06T2219/008
摘要： A system and method for providing user control of the projection of two-dimensional (2D) image information within the three-dimensional (3D) display space of a 3D-capable display device. Advantageously, the system and method disclosed herein allow a user to view 3D video even when the source video includes 2D content, by allowing the user to adjust the z-axis position of the 2D content, thereby causing the 2D content to be projected at a user-specified image depth within 3D space. The user can adjust the z-axis position of the 2D content in real time while contemporaneously viewing the imagery, e.g., via a remote control, and such adjustment can be stored for later use when similar or other 2D content is being viewed.
摘要翻译：一种系统和方法，用于提供对3D能力的显示设备的三维（3D）显示空间内的二维（2D）图像信息的投影的用户控制。有利地，本文公开的系统和方法允许用户通过允许用户调整2D内容的z轴位置，即使当源视频包括2D内容时也能够观看3D视频，从而使得2D内容被投射在 3D空间内用户指定的图像深度。用户可以在同时观看图像的同时实时地调整2D内容的z轴位置，例如通过遥控器，并且当正在观看类似的或其它2D内容时，这种调整可被存储以备以后使用。

10. 发明授权

US07460113B2 Digital pixel clock generation circuit and method employing independent clock 有权
标题翻译：采用独立时钟的数字像素时钟发生电路和方法
公开(公告)号：US07460113B2
公开(公告)日：2008-12-02
申请号：US10908429
申请日：2005-05-11
申请人： Philip Swan
发明人： Philip Swan
IPC分类号： G06F3/038
CPC分类号： G09G5/008 , H04N5/04 , H04N5/06 , H04N5/126 , H04N5/4401 , H04N5/70 , H04N21/4305
摘要： A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).
摘要翻译：数字像素时钟生成电路从至少一个外部图像源接收图像数据和对应的图像呈现时间信息。数字像素时钟产生电路包括：图像呈现定时错误确定电路，其基于预期呈现时间和实际呈现图像时间信息之间的差异来产生诸如像素输出时钟调整控制信息之类的期望像素时钟频率控制信息。可编程数字波形发生电路基于产生的期望像素时钟频率被编程，并且具有响应独立于外部图像源的时钟源的独立时钟源的输入。可编程数字波形发生电路提供独立生成的期望像素时钟的数字表示，然后将其输出到数模转换器（DAC）。

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