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1. 发明授权

US09653664B2 Chip substrate comprising a groove portion and chip package using the chip substrate 有权
公开(公告)号：US09653664B2
公开(公告)日：2017-05-16
申请号：US14753915
申请日：2015-06-29
申请人： Point Engineering Co., Ltd.
发明人： Sin Seok Han , Soo Young Choi , Ki Myung Nam
IPC分类号： H01L29/22 , H01L33/58 , H01L33/48 , H01L33/62 , H05K1/03 , H05K1/02
CPC分类号： H01L33/58 , H01L33/44 , H01L33/486 , H01L33/62
摘要： Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent. An existing typical adhesive agent may be used as it is. This provides an effect of saving costs. Thus, there is an advantage in that a low-priced existing bonding material may be applied to a high-priced UV-C (deep-UV) package.

2. 发明授权

US09378986B2 Method for mounting a chip and chip package 有权
标题翻译：安装芯片和芯片封装的方法
公开(公告)号：US09378986B2
公开(公告)日：2016-06-28
申请号：US14511353
申请日：2014-10-10
申请人： Point Engineering Co., Ltd.
发明人： Bum Mo Ahn , Ki Myung Nam , Seung Ho Park
IPC分类号： H01L23/495 , H01L21/56 , H01L23/00 , H01L21/48
CPC分类号： H01L21/563 , H01L21/4825 , H01L23/49513 , H01L23/4952 , H01L23/562 , H01L24/11 , H01L24/83 , H01L24/92 , H01L2224/1134 , H01L2224/1183 , H01L2224/13144 , H01L2224/291 , H01L2224/32013 , H01L2224/32227 , H01L2224/73265 , H01L2224/8314 , H01L2224/83192 , H01L2224/83385 , H01L2224/83815 , H01L2224/92227 , H01L2924/12041 , H01L2924/15156 , H01L2924/15787 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要： Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.
摘要翻译：提供了一种安装芯片的方法。该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

3. 发明申请

US20150102486A1 Method for Mounting a Chip and Chip Package 有权
标题翻译：安装芯片和芯片封装的方法
公开(公告)号：US20150102486A1
公开(公告)日：2015-04-16
申请号：US14511353
申请日：2014-10-10
申请人： Point Engineering Co., Ltd.
发明人： Bum Mo Ahn , Ki Myung Nam , Seung Ho Park
IPC分类号： H01L23/495 , H01L21/56 , H01L23/00
CPC分类号： H01L21/563 , H01L21/4825 , H01L23/49513 , H01L23/4952 , H01L23/562 , H01L24/11 , H01L24/83 , H01L24/92 , H01L2224/1134 , H01L2224/1183 , H01L2224/13144 , H01L2224/291 , H01L2224/32013 , H01L2224/32227 , H01L2224/73265 , H01L2224/8314 , H01L2224/83192 , H01L2224/83385 , H01L2224/83815 , H01L2224/92227 , H01L2924/12041 , H01L2924/15156 , H01L2924/15787 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要： Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.
摘要翻译：提供了一种安装芯片的方法。该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

4. 发明申请

US20140225135A1 Optical Device Array Substrate Having a Heat Dissipating Structure Integrated with a Substrate, and Method for Manufacturing Same 审中-公开
标题翻译：具有与基板一体化的散热结构的光学器件阵列基板及其制造方法相同
公开(公告)号：US20140225135A1
公开(公告)日：2014-08-14
申请号：US14343674
申请日：2012-07-26
申请人： Point Engineering Co., LTD
发明人： Bum Mo Ahn , Ki Myung Nam , Young Chul Jun
IPC分类号： H01L33/64
CPC分类号： H01L33/648 , H01L23/3677 , H01L23/4006 , H01L23/4093 , H01L33/642 , H01L2224/73265 , H01L2933/0075
摘要： The present invention relates to an optical device array substrate having a built-in heat dissipating structure, and to a method for manufacturing same, wherein the optical device array substrate itself is used as a heat sink and a coupling hole is formed at the bottom of the substrate to have a heat dissipating rod coupled thereto. The optical device array substrate having a built-in heat dissipating structure of the present invention consists essentially of: an optical device array substrate having a plurality of optical devices arranged on the top surface thereof and a plurality of coupling holes formed in the bottom surface thereof; and rod-shaped heat dissipating rods that have coupling projections formed on upper ends thereof, and are coupled to each of the coupling holes. In the above-described structure, the coupling holes are threaded, and the coupling projections are also threaded so as to be screw-coupled to the coupling holes. The coupling holes are formed having a downwardly narrowing taper, and the coupling projections are formed having a downwardly narrowing taper so as to be precisely coupled with the coupling holes even when in a contracted state under sub-freezing temperatures. The surfaces of the heat dissipating rods are characterized in that insulation coating layers are formed thereon and not on the coupling projections. A portion of the insulation coating layers on some of the heat dissipating rods may be removed to function as electrodes.
摘要翻译：本发明涉及具有内置散热结构的光学元件阵列基板及其制造方法，其中光学元件阵列基板本身用作散热器，并且在底部形成有耦合孔所述基板具有耦合到其上的散热杆。具有本发明的内置散热结构的光学元件阵列基板主要由以下部分组成：具有设置在其顶面上的多个光学元件的光学元件阵列基板和形成在其底面的多个连接孔 ; 杆状散热杆，其上部形成有联接突起，并且联接到每个连接孔。在上述结构中，联接孔是螺纹连接的，并且联接突起也是螺纹连接的，以便联接到联接孔。联接孔形成为具有向下变窄的锥形，并且联接突起形成为具有向下变窄的锥形，以便即使在亚冷冻温度下处于收缩状态下也能与联接孔精确耦合。散热棒的表面的特征在于其上形成有绝缘涂层，而不在耦合突起上。一些散热棒上的绝缘涂层的一部分可以被去除以用作电极。

5. 发明授权

US09537074B2 High heat-radiant optical device substrate 有权
标题翻译：高辐射光学器件基板
公开(公告)号：US09537074B2
公开(公告)日：2017-01-03
申请号：US14609112
申请日：2015-01-29
申请人： Point Engineering Co., Ltd.
发明人： Ki Myung Nam , Tae Hwan Song , Young Chul Jun
IPC分类号： B29C65/00 , B32B3/00 , B32B5/00 , B32B5/18 , B32B37/00 , H05K3/46 , B32B38/04 , C09J5/02 , B32B27/00 , B32B7/00 , B32B9/00 , B32B15/04 , B32B15/08 , B32B27/38 , H01L29/18 , H01L33/00 , H01L33/64 , H01L23/00 , H01L33/48 , H01L25/00 , B32B15/092 , B32B15/20 , B32B27/04 , B29C65/48 , H01L33/62
CPC分类号： H01L33/641 , B29C65/4835 , B32B15/092 , B32B15/20 , B32B27/04 , B32B2255/06 , B32B2255/26 , B32B2260/046 , H01L24/97 , H01L25/50 , H01L33/005 , H01L33/483 , H01L33/486 , H01L33/62 , H01L33/644 , H01L33/647 , H01L2224/73265 , H01L2924/12041 , H01L2933/0066 , H01L2933/0075 , Y10T428/24612 , Y10T428/31522 , Y10T428/31678
摘要： An optical device substrate includes metal plates and insulating layers formed between the metal plates. Each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate. The first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured insulating layer and the second metal and a fourth interface formed between the second anodized layer and the second metal.
摘要翻译：光学元件基板包括金属板和形成在金属板之间的绝缘层。每个绝缘层包括通过固化绝缘材料形成的固化绝缘层和与每个金属板合并的阳极氧化层，阳极氧化层通过阳极氧化每个金属板的第一金属和第二金属而形成。第一金属和第二金属分别包括第一阳极氧化层和第二阳极氧化层，并且通过界面电绝缘，所述界面包括形成在第一阳极氧化层和第一阳极氧化层之间的第一界面，形成在第一阳极氧化层固化的绝缘层，形成在固化的绝缘层和第二金属之间的第三界面和形成在第二阳极氧化层和第二金属之间的第四界面。

6. 发明申请

US20160190398A1 Substrate for Can Package-Type Optical Device and Optical Device using Same 审中-公开
标题翻译：可用于封装型光学器件的基板和使用相同的光学器件
公开(公告)号：US20160190398A1
公开(公告)日：2016-06-30
申请号：US14986092
申请日：2015-12-31
申请人： Point Engineering Co., Ltd.
发明人： Ki Myung Nam , Seung Ho Park , Tae Hwan Song
IPC分类号： H01L33/48 , H01L33/62
CPC分类号： H01L33/483 , H01L25/0753 , H01L33/486 , H01L33/56 , H01L33/62 , H01L2224/48091 , H01L2933/0033 , H01L2933/005 , H01L2933/0066 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to a method for manufacturing an optical device, and to an optical device manufactured thereby, which involve using a substrate itself as a heat-dissipating plate, and adopting a substrate with vertical insulation layers formed thereon, such that electrode terminals do not have to be extruded out from a sealed space, and thus enabling the overall structure and manufacturing process for an optical device to be simplified.According to the present invention, a method for manufacturing a can package-type optical device comprises the steps of: (a) preparing a metal plate and a metal substrate with vertical insulation layers, wherein more than one vertical insulation layer crossing the substrate from the top surface to the bottom surface thereof are formed; (b) bonding the metal plate on the top surface of the metal substrate with vertical insulation layers; (c) forming a cavity on an intermediate product that has undergone step (b) in a form of a cylindrical pit having a predetermined depth reaching the surface of said metal substrate with vertical insulation layers by passing through said metal plate and the adhesive layers formed by said bonding, wherein said cavity contains said vertical insulation layer in the bottom wall thereof; (e) connecting a wire, which electrically connects an optical device and an electrode of the optical device together, to either side of the surface of the bottom wall of the vertical insulation layers of the cavity, respectively; and (g) sealing the cavity by means of a protective plate made from a light-transmitting material; and a can cap, formed as a picture frame whose top central portion and the bottom are open and encompassing the perimeter of the protective plate.
摘要翻译：本发明涉及一种光学器件的制造方法及其制造的光学器件，其涉及使用基板本身作为散热板，并且采用其上形成有垂直绝缘层的基板，使得电极端子不必从密封空间挤出，从而能够简化光学装置的整体结构和制造过程。根据本发明，一种罐封装型光学器件的制造方法包括以下步骤：（a）制备具有垂直绝缘层的金属板和金属基板，其中多于一个垂直绝缘层与形成其底面的顶面; （b）用垂直绝缘层将金属板与金属基板的顶面接合; （c）在具有预定深度的圆柱形凹坑形式的步骤（b）中形成空腔，该预定深度通过穿过所述金属板并形成的粘合剂层到达所述金属基板的具有垂直绝缘层的表面通过所述接合，其中所述空腔在其底壁中包含所述垂直绝缘层; （e）将将光学装置和光学装置的电极电连接在一起的导线分别连接到腔的垂直绝缘层的底壁的表面的任一侧; 和（g）通过由透光材料制成的保护板密封空腔; 以及罐盖，其形成为其顶部中心部分和底部打开并且包围保护板的周边的相框。

7. 发明申请

US20150147580A1 High Heat-Radiant Optical Device Substrate 有权
标题翻译：高热辐射光学器件基板
公开(公告)号：US20150147580A1
公开(公告)日：2015-05-28
申请号：US14609112
申请日：2015-01-29
申请人： Point Engineering Co., Ltd.
发明人： Ki Myung Nam , Tae Hwan Song , Young Chul Jun
IPC分类号： H01L33/64
CPC分类号： H01L33/641 , B29C65/4835 , B32B15/092 , B32B15/20 , B32B27/04 , B32B2255/06 , B32B2255/26 , B32B2260/046 , H01L24/97 , H01L25/50 , H01L33/005 , H01L33/483 , H01L33/486 , H01L33/62 , H01L33/644 , H01L33/647 , H01L2224/73265 , H01L2924/12041 , H01L2933/0066 , H01L2933/0075 , Y10T428/24612 , Y10T428/31522 , Y10T428/31678
摘要： An optical device substrate includes metal plates and insulating layers formed between the metal plates. Each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate. The first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured insulating layer and the second metal and a fourth interface formed between the second anodized layer and the second metal.
摘要翻译：光学元件基板包括金属板和形成在金属板之间的绝缘层。每个绝缘层包括通过固化绝缘材料形成的固化绝缘层和与每个金属板合并的阳极氧化层，阳极氧化层通过阳极氧化每个金属板的第一金属和第二金属而形成。第一金属和第二金属分别包括第一阳极氧化层和第二阳极氧化层，并且通过界面电绝缘，所述界面包括形成在第一阳极氧化层和第一阳极氧化层之间的第一界面，形成在第一阳极氧化层固化的绝缘层，形成在固化的绝缘层和第二金属之间的第三界面和形成在第二阳极氧化层和第二金属之间的第四界面。

8. 发明申请

US20140374783A1 Optical Device Integrated with Driving Circuit and Power Supply Circuit, Method for Manufacturing Optical Device Substrate Used Therein, and Substrate Thereof 有权
标题翻译：与驱动电路和电源电路集成的光学器件，其中使用的光学器件基板及其基板的制造方法
公开(公告)号：US20140374783A1
公开(公告)日：2014-12-25
申请号：US14365408
申请日：2012-10-04
申请人： Point Engineering Co., Ltd.
发明人： Bum Mo Ahn , Ki Myung Nam , Seung Ho Park
IPC分类号： H01L27/15 , H01L33/64 , H01L33/62 , H01L33/00
CPC分类号： H01L27/15 , H01L25/0753 , H01L25/167 , H01L33/005 , H01L33/62 , H01L33/64 , H01L2224/48091 , H01L2224/48465 , H05B33/0803 , H05B33/0806 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to an optical device integrated with a driving circuit and a power supply circuit, a method for manufacturing an optical device substrate used therein, and a substrate thereof, which are capable of reducing the overall size and facilitating the handling and management thereof by mounting a plurality of optical elements, driving circuits thereof, and power supply circuits thereof on a single substrate for an optical device having a vertical insulating layer. The objective of the present invention is to provide the optical device integrated with the driving circuit and the power supply circuit, the method for manufacturing the optical device substrate used therein, and the substrate thereof which are capable of reducing the overall size and facilitating the handling and the management thereof by mounting the plurality of optical elements, the driving circuits thereof, and the power supply circuits thereof on the single substrate for the optical device having the vertical insulating layer.
摘要翻译：本发明涉及与驱动电路和电源电路集成的光学器件，其中使用的光学器件衬底的制造方法及其基板，其能够减小总体尺寸并且便于其处理和管理通过将多个光学元件，其驱动电路及其电源电路安装在具有垂直绝缘层的光学器件的单个基板上。本发明的目的是提供与驱动电路和电源电路集成的光学装置，其中使用的光学器件基板的制造方法及其基板，其能够减小总体尺寸并便于处理并且通过将多个光学元件及其驱动电路及其电源电路安装在具有垂直绝缘层的光学器件的单个基板上来进行管理。

9. 发明授权

US09818913B2 Chip substrate 有权
公开(公告)号：US09818913B2
公开(公告)日：2017-11-14
申请号：US15420705
申请日：2017-01-31
申请人： Point Engineering Co., Ltd.
发明人： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
IPC分类号： H01L33/54 , H01L33/44 , H01L33/62 , H01L33/48 , H01L33/58
CPC分类号： H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
摘要： A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.

10. 发明授权

US09666558B2 Substrate for mounting a chip and chip package using the substrate 有权
公开(公告)号：US09666558B2
公开(公告)日：2017-05-30
申请号：US14753807
申请日：2015-06-29
申请人： POINT ENGINEERING CO., LTD.
发明人： Bum Mo Ahn , Ki Myung Nam , Seung Ho Park
IPC分类号： H01L25/065 , H01L23/498
CPC分类号： H01L25/065 , H01L23/49811 , H01L23/49838 , H01L25/18 , H01L2225/06517 , H01L2225/06524
摘要： Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted, a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions, and a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted.

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