专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150255614A1 SPLIT GATE FLASH MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：分闸门闪存及其制造方法
公开(公告)号：US20150255614A1
公开(公告)日：2015-09-10
申请号：US14197234
申请日：2014-03-05
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai , Ikuo Kurachi
IPC分类号： H01L29/788 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7889 , H01L27/11524 , H01L29/42328 , H01L29/42336 , H01L29/4236 , H01L29/66825 , H01L29/7885
摘要： A split gate flash memory is provided. A device isolation structure is disposed in a substrate to define an active area. A first doping region and a second doping region are respectively disposed in an active area of the substrate. A select gate is disposed in a trench in the substrate, and a side of the select gate is adjacent to the first doping region. A gate dielectric layer is disposed between the select gate and the substrate. A floating gate is disposed on the substrate, a side of the floating gate overlaps to the second doping region, and a portion of the floating gate is disposed on the select gate. An inter-gate dielectric layer is disposed between the floating gate and the select gate and between the floating gate and the substrate.
摘要翻译：提供了分闸门闪存。器件隔离结构设置在衬底中以限定有源区域。第一掺杂区域和第二掺杂区域分别设置在衬底的有源区域中。选择栅极设置在衬底中的沟槽中，并且选择栅极的一侧与第一掺杂区相邻。栅极电介质层设置在选择栅极和衬底之间。浮置栅极设置在衬底上，浮置栅极的一侧与第二掺杂区域重叠，并且浮置栅极的一部分设置在选择栅极上。栅极间电介质层设置在浮置栅极和选择栅极之间以及浮置栅极和衬底之间。

2. 发明申请

US20140256104A1 MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY 审中-公开
标题翻译：垂直通道晶体管阵列的制造方法
公开(公告)号：US20140256104A1
公开(公告)日：2014-09-11
申请号：US14271400
申请日：2014-05-06
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.
摘要翻译：提供了一种垂直沟道晶体管阵列的制造方法。该方法包括以下步骤。多个嵌入字线形成在沟槽的底部，并且每个嵌入字线位于沟槽之一的第一侧壁处，并连接到同一行中的半导体柱的第一侧。每个嵌入字线不连接到同一行中的半导体柱的第二侧，并且第一侧与第二侧相对。只有一个嵌入字线相应地连接到排成一行的半导体柱。在每个沟槽的第二侧壁和每个嵌入字线之间形成隔离结构。第一侧壁与第二侧壁相对。

3. 发明申请

US20130130471A1 MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY 有权
标题翻译：垂直通道晶体管阵列的制造方法
公开(公告)号：US20130130471A1
公开(公告)日：2013-05-23
申请号：US13745867
申请日：2013-01-21
申请人： POWERCHIP TECHNOLOGY CORPORATION
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L21/762
CPC分类号： H01L21/762 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
摘要翻译：垂直沟道晶体管阵列具有由多个半导体柱形成的有源区。多个嵌入式位线平行布置在半导体衬底中并沿列方向延伸。多个位线触点分别设置在一个嵌入位线的一侧。多个嵌入字线平行地布置在嵌入式位线上方并沿行方向延伸。此外，嵌入字线将同一行中的半导体柱与夹在嵌入字线和半导体柱之间的栅介质层连接。电流泄漏隔离结构设置在嵌入式位线的端子处，以防止相邻位线触点之间的电流泄漏。

4. 发明申请

US20150340427A1 CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：电容器结构及其制造方法
公开(公告)号：US20150340427A1
公开(公告)日：2015-11-26
申请号：US14497345
申请日：2014-09-26
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai , Hui-Huang Chen , Ching-Hua Chen , Ying-Chia Lin
IPC分类号： H01L49/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53295 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure including at least one capacitor unit is provided. The capacitor unit includes a dielectric layer, an inner metal layer and an outer metal layer. The inner metal layer is disposed in the dielectric layer. The outer metal layer is disposed in the dielectric layer and surrounds the inner metal layer. The outer metal layer includes a first metal layer, two second metal layers and a third metal layer. The first metal layer is disposed under the inner metal layer. The second metal layers are disposed at two sides of the inner metal layer, and lower surfaces of the second metal layers are located equal to or below a lower surface of the inner metal layer. The third metal layer is disposed over the inner metal layer and connects to the second metal layers.
摘要翻译：提供了包括至少一个电容器单元的电容器结构。电容器单元包括电介质层，内金属层和外金属层。内部金属层设置在电介质层中。外部金属层设置在电介质层中并且围绕内部金属层。外金属层包括第一金属层，第二金属层和第三金属层。第一金属层设置在内金属层的下方。第二金属层设置在内金属层的两侧，第二金属层的下表面位于内金属层的下表面的下方。第三金属层设置在内金属层上并连接到第二金属层。

5. 发明授权

US09536890B2 Semiconductor transistor and flash memory, and manufacturing method thereof 有权
标题翻译：半导体晶体管和闪存及其制造方法
公开(公告)号：US09536890B2
公开(公告)日：2017-01-03
申请号：US14675754
申请日：2015-04-01
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/115 , H01L29/788 , H01L29/78 , H01L29/51 , H01L29/66
CPC分类号： H01L27/11526 , H01L21/2652 , H01L21/26586 , H01L27/11519 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L29/4925 , H01L29/4983 , H01L29/513 , H01L29/66492 , H01L29/6659 , H01L29/66825 , H01L29/7833 , H01L29/7836 , H01L29/788
摘要： A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties.
摘要翻译：设置在基板上的闪存。闪速存储器包括包括堆叠的栅极结构，轻掺杂区域和间隔物的半导体晶体管。堆叠的栅极结构包括顺序地设置在衬底上的栅介质层，第一导电层，电介质层和第二导电层。电介质层在其周围具有开口，使得第一导电层与第二导电层电连接。轻掺杂区域在堆叠栅极结构的侧面处的开口下方设置在基板中。间隔件设置在堆叠的门结构的侧壁上。通过控制开口下方的第一导电层的高度来调节间隔物的宽度。通过使用电介质层作为掩模层来设置轻掺杂区域，以便获得轻掺杂区域的边缘以获得良好的电性能。

6. 发明授权

US09484349B1 Static random access memory 有权
标题翻译：静态随机存取存储器
公开(公告)号：US09484349B1
公开(公告)日：2016-11-01
申请号：US14924729
申请日：2015-10-28
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/11
CPC分类号： H01L27/1104
摘要： A static random access memory (SRAM) including at least a SRAM cell is provided. A gate layout of the SRAM cell includes first to fourth strip doped regions, a recessed gate line and first and second gate lines. The first to fourth strip doped regions are disposed in the substrate in order and separated from each other. The recessed gate line intersects the first to fourth strip doped regions. The first to fourth strip doped regions are disconnected at intersections with the recessed gate line. The first gate line intersects the first and the second strip doped regions. The first and the second strip doped regions are disconnected at intersections with the first gate line. The second gate line intersects the third the fourth strip doped regions. The third and the fourth strip dopeds region are disconnected at intersections with the second gate line.
摘要翻译：提供至少包括SRAM单元的静态随机存取存储器（SRAM）。 SRAM单元的栅极布局包括第一至第四条带掺杂区域，凹入栅极线以及第一和第二栅极线。第一至第四带状掺杂区域依次布置在衬底中并彼此分离。凹入的栅极线与第一至第四条带掺杂区相交。第一至第四条带掺杂区域在与凹入栅极线的交叉处断开。第一栅极线与第一和第二条带掺杂区相交。第一和第二条带掺杂区域在与第一栅极线交叉处断开。第二栅极线与第四条带掺杂区域相交。第三和第四条带掺杂区域在与第二栅极线交叉处断开。

7. 发明授权

US08536008B2 Manufacturing method of vertical channel transistor array 有权
标题翻译：垂直沟道晶体管阵列的制造方法
公开(公告)号：US08536008B2
公开(公告)日：2013-09-17
申请号：US13745867
申请日：2013-01-21
申请人： Powerchip Technology Corporation
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L21/336
CPC分类号： H01L21/762 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
摘要翻译：垂直沟道晶体管阵列具有由多个半导体柱形成的有源区。多个嵌入式位线平行布置在半导体衬底中并沿列方向延伸。多个位线触点分别设置在一个嵌入位线的一侧。多个嵌入字线平行地布置在嵌入式位线上方并沿行方向延伸。此外，嵌入字线将同一行中的半导体柱与夹在嵌入字线和半导体柱之间的栅介质层连接。电流泄漏隔离结构设置在嵌入式位线的端子处，以防止相邻位线触点之间的电流泄漏。

8. 发明授权

US09576963B2 Manufacturing method of vertical channel transistor array 有权
标题翻译：垂直沟道晶体管阵列的制造方法
公开(公告)号：US09576963B2
公开(公告)日：2017-02-21
申请号：US14271400
申请日：2014-05-06
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.
摘要翻译：提供了一种垂直沟道晶体管阵列的制造方法。该方法包括以下步骤。多个嵌入字线形成在沟槽的底部，并且每个嵌入字线位于沟槽之一的第一侧壁处并连接到同一行中的半导体柱的第一侧。每个嵌入字线不连接到同一行中的半导体柱的第二侧，并且第一侧与第二侧相对。只有一个嵌入字线相应地连接到排成一行的半导体柱。在每个沟槽的第二侧壁和每个嵌入字线之间形成隔离结构。第一侧壁与第二侧壁相对。

9. 发明申请

US20160293616A1 SEMICONDUCTOR TRANSISTOR AND FLASH MEMORY, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体晶体管和闪存存储器及其制造方法
公开(公告)号：US20160293616A1
公开(公告)日：2016-10-06
申请号：US14675754
申请日：2015-04-01
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/115 , H01L29/66 , H01L29/51 , H01L29/788 , H01L29/78
CPC分类号： H01L27/11526 , H01L21/2652 , H01L21/26586 , H01L27/11519 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L29/4925 , H01L29/4983 , H01L29/513 , H01L29/66492 , H01L29/6659 , H01L29/66825 , H01L29/7833 , H01L29/7836 , H01L29/788
摘要： A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties.
摘要翻译：设置在基板上的闪存。闪速存储器包括包括堆叠的栅极结构，轻掺杂区域和间隔物的半导体晶体管。堆叠的栅极结构包括顺序地设置在衬底上的栅介质层，第一导电层，电介质层和第二导电层。电介质层在其周围具有开口，使得第一导电层与第二导电层电连接。轻掺杂区域在堆叠栅极结构的侧面处的开口下方设置在基板中。间隔件设置在堆叠的门结构的侧壁上。通过控制开口下方的第一导电层的高度来调节间隔物的宽度。通过使用电介质层作为掩模层来设置轻掺杂区域，以便获得轻掺杂区域的边缘以获得良好的电性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式