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1. 发明授权

US09602317B1 Apparatus and method for combining currents from passive equalizer in sense amplifier 有权
公开(公告)号：US09602317B1
公开(公告)日：2017-03-21
申请号：US14880916
申请日：2015-10-12
申请人： QUALCOMM Incorporated
发明人： Eskinder Hailu , Hanan Cohen , Bupesh Pandita
IPC分类号： H04L25/06 , H04L25/10 , H04L25/03 , H04B1/04
CPC分类号： H04L25/03885 , G11C7/062 , G11C7/065 , G11C7/1084 , H03F3/24 , H03F3/45183 , H03F2203/45352 , H03F2203/45544 , H03F2203/45591 , H03F2203/45644 , H03G5/005 , H03G5/24 , H04B3/18
摘要： An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.

2. 发明授权

US09484900B2 Digital-to-phase converter 有权
标题翻译：数模转换器
公开(公告)号：US09484900B2
公开(公告)日：2016-11-01
申请号：US14535744
申请日：2014-11-07
申请人： QUALCOMM Incorporated
发明人： Hanan Cohen
IPC分类号： H03H11/16 , H03K5/135 , H03L7/00 , H03L7/081 , H03K5/00
CPC分类号： H03K5/135 , H03K2005/00286 , H03L7/00 , H03L7/0812
摘要： Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.
摘要翻译：公开了将数字信号转换成时钟相位的系统和方法。一个示例性数字 - 相位转换器电路接收互补的同相和正交时钟信号，并在由数字相位控制输入控制的相位产生四个时钟输出。数/模转换器使用第一和第二预驱动器模块来缓冲相位和正交时钟信号，并产生具有受控转换速率的对应缓冲时钟信号。混频器模块通过形成缓冲时钟信号的加权组合来产生时钟输出。加权根据相位控制输入确定。缓冲时钟信号的受控转换速率允许数字混频器模块提供精确的相位控制。数/模转换器还可以包括输出缓冲器，其补偿时钟输出的相位和相位控制输入之间的关系中的非线性。

3. 发明申请

US20170222789A1 COMPACT PHASE INTERPOLATOR 有权
公开(公告)号：US20170222789A1
公开(公告)日：2017-08-03
申请号：US15013914
申请日：2016-02-02
申请人： QUALCOMM Incorporated
发明人： Eskinder Hailu , Hanan Cohen , Li Sun , Zhiqin Chen
IPC分类号： H04L7/00
CPC分类号： H04L7/0025 , H03H11/22 , H03H17/08 , H03K5/13 , H03K5/131 , H03K5/135
摘要： A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

4. 发明申请

US20170041005A1 NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
标题翻译：新的相位锁相环（PLL）架构
公开(公告)号：US20170041005A1
公开(公告)日：2017-02-09
申请号：US14820894
申请日：2015-08-07
申请人： QUALCOMM Incorporated
发明人： Bupesh Pandita , Hanan Cohen , Eskinder Hailu , Kenneth Luis Arcudia
IPC分类号： H03K21/10
CPC分类号： H03K21/10 , H03L7/18 , H03L7/197 , H03L7/1974 , H03L7/1976
摘要： In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
摘要翻译：在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地当模数信号传播到分频器级之后的负载信号。该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

5. 发明申请

US20160134266A1 DIGITAL-TO-PHASE CONVERTER 有权
标题翻译：数字到相位转换器
公开(公告)号：US20160134266A1
公开(公告)日：2016-05-12
申请号：US14535744
申请日：2014-11-07
申请人： QUALCOMM Incorporated
发明人： Hanan Cohen
IPC分类号： H03K5/135 , H03L7/081
CPC分类号： H03K5/135 , H03K2005/00286 , H03L7/00 , H03L7/0812
摘要： Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.
摘要翻译：公开了将数字信号转换成时钟相位的系统和方法。一个示例性数字 - 相位转换器电路接收互补的同相和正交时钟信号，并在由数字相位控制输入控制的相位产生四个时钟输出。数/模转换器使用第一和第二预驱动器模块来缓冲相位和正交时钟信号，并产生具有受控转换速率的对应缓冲时钟信号。混频器模块通过形成缓冲时钟信号的加权组合来产生时钟输出。加权根据相位控制输入确定。缓冲时钟信号的受控转换速率允许数字混频器模块提供精确的相位控制。数/模转换器还可以包括输出缓冲器，其补偿时钟输出的相位和相位控制输入之间的关系中的非线性。

6. 发明申请

US20170104616A1 APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER IN SENSE AMPLIFIER 有权
公开(公告)号：US20170104616A1
公开(公告)日：2017-04-13
申请号：US14880916
申请日：2015-10-12
申请人： QUALCOMM Incorporated
发明人： Eskinder Hailu , Hanan Cohen , Bupesh Pandita
IPC分类号： H04L25/03 , H04B1/04
CPC分类号： H04L25/03885 , G11C7/062 , G11C7/065 , G11C7/1084 , H03F3/24 , H03F3/45183 , H03F2203/45352 , H03F2203/45544 , H03F2203/45591 , H03F2203/45644 , H03G5/005 , H03G5/24 , H04B3/18
摘要： An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.

7. 发明授权

US09755817B2 Compact phase interpolator 有权
公开(公告)号：US09755817B2
公开(公告)日：2017-09-05
申请号：US15013914
申请日：2016-02-02
申请人： QUALCOMM Incorporated
发明人： Eskinder Hailu , Hanan Cohen , Li Sun , Zhiqin Chen
IPC分类号： H04L7/00 , H03K5/13 , H03K5/135 , H03K5/131 , H03H17/08 , H03H11/22
CPC分类号： H04L7/0025 , H03H11/22 , H03H17/08 , H03K5/13 , H03K5/131 , H03K5/135
摘要： A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

8. 发明申请

US20170149555A1 SELF-TEST FOR SOURCE-SYNCHRONOUS INTERFACE 审中-公开
公开(公告)号：US20170149555A1
公开(公告)日：2017-05-25
申请号：US14947278
申请日：2015-11-20
申请人： QUALCOMM Incorporated
发明人： Hanan Cohen , Jason Thurston
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0332 , H04L1/205 , H04L1/243 , H04L7/0008 , H04L7/0012 , H04L7/0025 , H04L7/0334 , H04L7/0337
摘要： A source-synchronous system is provided in which a master device is configured to vary the phase between a transmitted data signal and a corresponding source-synchronous clock to measure the margins of a data eye at a slave device.

9. 发明授权

US09577646B1 Fractional phase locked loop (PLL) architecture 有权
标题翻译：分数锁相环（PLL）架构
公开(公告)号：US09577646B1
公开(公告)日：2017-02-21
申请号：US14820894
申请日：2015-08-07
申请人： QUALCOMM Incorporated
发明人： Bupesh Pandita , Hanan Cohen , Eskinder Hailu , Kenneth Luis Arcudia
IPC分类号： H03K21/10
CPC分类号： H03K21/10 , H03L7/18 , H03L7/197 , H03L7/1974 , H03L7/1976
摘要： In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
摘要翻译：在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地当模数信号传播到分频器级之后的负载信号。该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

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