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1. 发明授权

US09411727B2 Split write operation for resistive memory cache 有权
标题翻译：电阻式存储器高速缓存的分割写操作
公开(公告)号：US09411727B2
公开(公告)日：2016-08-09
申请号：US14963201
申请日：2015-12-08
申请人： QUALCOMM INCORPORATED
发明人： Xiangyu Dong , Xiaochun Zhu , Jungwon Suh
IPC分类号： G06F12/08 , G11C7/10 , G11C11/16 , G06F13/00
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/22 , G06F2212/222 , G06F2212/60 , G11C7/1015 , G11C7/1039 , G11C7/1084 , G11C11/165 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C2207/2245 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
摘要翻译：读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。

2. 发明授权

US09275714B1 Read operation of MRAM using a dummy word line 有权
标题翻译：使用虚拟字线读取MRAM的操作
公开(公告)号：US09275714B1
公开(公告)日：2016-03-01
申请号：US14499050
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Sungryul Kim , Jung Pill Kim , Xiangyu Dong
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1693
摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM). Prior to determining whether there is a hit in the MRAM for a first address corresponding to the read operation, a dummy word line is activated, based on at least a subset of bits of the first address. A settling process for a reference voltage for reading MRAM bit cells at the first address is initiated, based on dummy cells connected to the dummy word line and a settled reference voltage is obtained. If there is a hit, a first word line is activated based on a row address determined from the first address, and the MRAM bit cells at the first address are read using the settled reference voltage.
摘要翻译：系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的位的至少一个子集，激活伪字线。基于与虚拟字线连接的虚拟单元，启动用于读取第一地址的MRAM位单元的参考电压的稳定处理，并获得稳定的参考电压。如果存在命中，则基于从第一地址确定的行地址来激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

3. 发明授权

US09239788B2 Split write operation for resistive memory cache 有权
公开(公告)号：US09239788B2
公开(公告)日：2016-01-19
申请号：US14062558
申请日：2013-10-24
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong , Xiaochun Zhu , Jungwon Suh
IPC分类号： G06F12/08 , G11C7/10 , G11C11/16 , G06F13/00
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/22 , G06F2212/222 , G06F2212/60 , G11C7/1015 , G11C7/1039 , G11C7/1084 , G11C11/165 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C2207/2245 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

4. 发明授权

US09196339B2 Resistance-based memory cells with multiple source lines 有权
标题翻译：具有多个源极线的基于电阻的存储单元
公开(公告)号：US09196339B2
公开(公告)日：2015-11-24
申请号：US14041868
申请日：2013-09-30
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong
IPC分类号： G11C11/16 , G11C7/10 , G11C8/16 , G11C11/00 , G11C11/56 , G11C13/00 , G11C17/02 , G11C17/14
CPC分类号： G11C11/1673 , G11C7/1075 , G11C8/16 , G11C11/005 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C11/5671 , G11C13/0002 , G11C17/02 , G11C17/14 , G11C2213/74 , G11C2213/79
摘要： In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
摘要翻译：在特定实施例中，器件包括具有多个源极线和多个存取晶体管的基于电阻的存储单元。多个存取晶体管与多个源极线的耦合配置对数据值进行编码。

5. 发明申请

US20140177325A1 INTEGRATED MRAM MODULE 有权
标题翻译：集成MRAM模块
公开(公告)号：US20140177325A1
公开(公告)日：2014-06-26
申请号：US13721092
申请日：2012-12-20
申请人： QUALCOMM INCORPORATED
发明人： Xiangyu Dong , Jung Pill Kim , Jungwon Suh
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1653 , G11C2211/5643 , Y10T29/49117
摘要： Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.
摘要翻译：用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或多个包装。第二包还包括存储器控制器逻辑。简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的封印能力。

6. 发明授权

US09911485B2 Method and apparatus for refreshing a memory cell 有权
公开(公告)号：US09911485B2
公开(公告)日：2018-03-06
申请号：US14244173
申请日：2014-04-03
申请人： QUALCOMM Incorporated
发明人： Deepti Vijayalakshmi Sriramagiri , Jung Pill Kim , Jungwon Suh , Xiangyu Dong
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40626 , G11C2211/406
摘要： A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

7. 发明授权

US09431129B2 Variable read delay system 有权
标题翻译：可变读延迟系统
公开(公告)号：US09431129B2
公开(公告)日：2016-08-30
申请号：US14266326
申请日：2014-04-30
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Xiangyu Dong
IPC分类号： G11C29/02 , G11C29/30 , G11C7/10 , G11C16/26 , G11C16/30 , G11C14/00 , G06F11/10 , G11C29/52 , G11C7/06 , G11C7/08 , G11C29/04 , G11C11/16 , G11C13/00
CPC分类号： G11C29/026 , G06F11/106 , G06F11/1072 , G06F11/1076 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1072 , G11C11/16 , G11C11/1673 , G11C13/004 , G11C14/0081 , G11C14/009 , G11C16/26 , G11C16/30 , G11C29/30 , G11C29/52 , G11C2029/0411
摘要： A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.
摘要翻译：一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。第二感测延迟比第一感测延迟更长。

8. 发明授权

US09368187B2 Insertion-override counter to support multiple memory refresh rates 有权
标题翻译：插入覆盖计数器，以支持多个内存刷新率
公开(公告)号：US09368187B2
公开(公告)日：2016-06-14
申请号：US14149543
申请日：2014-01-07
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong , Jung Pill Kim
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40618 , G11C11/40611 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations.
摘要翻译：存储器刷新方法包括确定在存储器块的正常行的规则调度的刷新操作中插入存储器块的弱行的刷新操作的位置。刷新操作以基本恒定的刷新率发生。要插入的位置基于实际的弱页面地址。该方法还包括在所确定的位置处执行插入的刷新操作，以协调在规则排列的刷新操作之间插入的刷新操作的分布。

9. 发明授权

US09348743B2 Inter-set wear-leveling for caches with limited write endurance 有权
标题翻译：具有有限写入耐力的缓存的集成磨损均衡
公开(公告)号：US09348743B2
公开(公告)日：2016-05-24
申请号：US13772400
申请日：2013-02-21
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0238 , G06F12/0246 , G06F12/0802 , G06F12/0864 , G06F12/0891 , G06F2212/7211
摘要： A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.
摘要翻译：高速缓存控制器包括第一寄存器，其在每个存储器位置交换操作之后更新高速缓冲存储器中的多个高速缓存组并且重置每个N-1个存储器位置交换操作。 N是高速缓冲存储器中的多个缓存集合。存储器控制器还具有在每N-1个存储器位置交换操作之后更新的第二寄存器，并且重置每个（N2-N）个存储器位置交换操作。第一和第二寄存器跟踪高速缓存集合的逻辑位置和物理位置之间的关系。

10. 发明授权

US09299457B2 Kernel masking of DRAM defects 有权
标题翻译： DRAM缺陷的内核屏蔽
公开(公告)号：US09299457B2
公开(公告)日：2016-03-29
申请号：US14187279
申请日：2014-02-23
申请人： QUALCOMM INCORPORATED
发明人： Dexter T. Chun , Yanru Li , Xiangyu Dong , Jungwon Suh , Jung Pill Kim , Deepti Vijayalakshmi Sriramagiri
IPC分类号： G11C29/00 , G11C29/44 , G06F11/10 , G06F11/20 , G06F12/02
CPC分类号： G11C29/44 , G06F11/1048 , G06F11/1076 , G06F11/2053 , G06F12/0246 , G06F2212/7209 , G11C2029/4402
摘要： Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.
摘要翻译：公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。

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