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1. 发明授权

US10553531B2 Process-invariant resistor and capacitor pair 有权
公开(公告)号：US10553531B2
公开(公告)日：2020-02-04
申请号：US15710737
申请日：2017-09-20
申请人： QUALCOMM Incorporated
发明人： Chao Song , Xuhao Huang , Marzio Pedrali-Noy
IPC分类号： H01L23/522 , H01P1/203 , H05K3/30 , H01L21/74 , H01L21/82 , H01L27/01 , H01L49/02
摘要： A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer capacitor each having a plurality of longitudinally-extending fingers having the same width and separation.

2. 发明申请

US20140347941A1 LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM 有权
标题翻译：用于MESOCHRONOUS DDR系统的低延迟同步方案
公开(公告)号：US20140347941A1
公开(公告)日：2014-11-27
申请号：US13902705
申请日：2013-05-24
申请人： QUALCOMM Incorporated
发明人： Edwin Jose , Michael Drop , Xuhao Huang , Raghu Sankuratri , Deepti Sriramagiri , Marzio Pedrali-Noy
IPC分类号： G11C7/22
CPC分类号： G11C11/4076 , G06F13/1689 , G11C7/1084 , G11C7/1093 , G11C7/222 , G11C11/4093 , G11C2207/2254 , H03L7/093 , Y02D10/14
摘要： In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.
摘要翻译：在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的时钟信号。

3. 发明申请

US20140029611A1 SYSTEMS AND METHODS FOR SHARING A SERIAL COMMUNICATION PORT BETWEEN A PLURALITY OF COMMUNICATION CHANNELS 有权
标题翻译：在多个通信信道之间共享串行通信端口的系统和方法
公开(公告)号：US20140029611A1
公开(公告)日：2014-01-30
申请号：US13841355
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Xuhao Huang , Ankit Srivastava , Xiaohong Quan , Seyfollah S. Bazarjani
IPC分类号： H04L12/947
CPC分类号： H04L49/25 , H04L12/40006 , H04L12/4035 , H04L25/0272
摘要： An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.
摘要翻译：描述了用于在多个通信信道之间共享串行通信端口的装置。该装置包括管理串行通信端口上的通信的收发器。该设备还包括耦合到收发器的多路复用器，其中复用器复用多个通信信道。该装置还包括耦合到多路复用器的识别信息电路，其中识别信息电路将识别信息添加到来自多个通信信道的数据，使多个通信信道能够共享串行通信端口。串行通信端口和多路复用器允许在多个通信信道有效时满足多个通信信道的至少一个等待时间度量的集成电路之间的通信。

4. 发明授权

US11196410B2 Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权
公开(公告)号：US11196410B2
公开(公告)日：2021-12-07
申请号：US17022608
申请日：2020-09-16
申请人： QUALCOMM Incorporated
发明人： Zhengzheng Wu , Xu Zhang , Xuhao Huang
IPC分类号： H03K5/134 , H03K3/03 , H03K5/00
摘要： A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

5. 发明授权

US10185337B1 Low-power temperature-insensitive current bias circuit 有权
公开(公告)号：US10185337B1
公开(公告)日：2019-01-22
申请号：US15945568
申请日：2018-04-04
申请人： QUALCOMM Incorporated
发明人： Sungmin Ock , Wenjing Yin , Xuhao Huang
IPC分类号： G05F1/46 , H03K17/687
摘要： A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.

6. 发明授权

US09437278B2 Low latency synchronization scheme for mesochronous DDR system 有权
标题翻译：用于中间同步DDR系统的低延迟同步方案
公开(公告)号：US09437278B2
公开(公告)日：2016-09-06
申请号：US14816820
申请日：2015-08-03
申请人： QUALCOMM Incorporated
发明人： Edwin Jose , Michael Drop , Xuhao Huang , Raghu Sankuratri , Deepti Vijayalakshmi Sriramagiri , Marzio Pedrali-Noy
IPC分类号： G11C11/4076 , H03L7/093 , G11C7/22 , G06F13/16 , G11C7/10 , G11C11/4093
CPC分类号： G11C11/4076 , G06F13/1689 , G11C7/1084 , G11C7/1093 , G11C7/222 , G11C11/4093 , G11C2207/2254 , H03L7/093 , Y02D10/14
摘要： A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.
摘要翻译：根据某些实施例提供了用于数据同步的方法。该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期方向。

7. 发明授权

US10812056B1 Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权
公开(公告)号：US10812056B1
公开(公告)日：2020-10-20
申请号：US16722572
申请日：2019-12-20
申请人： QUALCOMM Incorporated
发明人： Zhengzheng Wu , Xu Zhang , Xuhao Huang
IPC分类号： H03K5/134 , H03K3/03 , H03K5/00
摘要： A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

8. 发明申请

US20190089030A1 PROCESS-INVARIANT RESISTOR AND CAPACITOR PAIR 审中-公开
公开(公告)号：US20190089030A1
公开(公告)日：2019-03-21
申请号：US15710737
申请日：2017-09-20
申请人： QUALCOMM Incorporated
发明人： Chao Song , Xuhao Huang , Marzio Pedrali-Noy
IPC分类号： H01P1/203 , H05K3/30 , H01L21/82 , H01L21/74
摘要： A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer capacitor each having a plurality of longitudinally-extending fingers having the same width and separation.

9. 发明授权

US09973081B1 Low-power low-duty-cycle switched-capacitor voltage divider 有权
公开(公告)号：US09973081B1
公开(公告)日：2018-05-15
申请号：US15680105
申请日：2017-08-17
申请人： QUALCOMM Incorporated
发明人： Wenjing Yin , Xuhao Huang , Sungmin Ock
IPC分类号： H02M3/07 , H02M1/08
CPC分类号： H02M3/07 , H02M1/08 , H02M2003/072
摘要： A switched-capacitor voltage divider is provided that functions to divide an input voltage only while a low-duty-cycle clock pulse signal is asserted. All the switches in the switched-capacitor voltage divider are idle during an off time for the low-duty-cycle clock pulse signal.

10. 发明申请

US20150364170A1 DISTRIBUTED CLOCK SYNCHRONIZATION 有权
标题翻译：分布式时钟同步
公开(公告)号：US20150364170A1
公开(公告)日：2015-12-17
申请号：US14302727
申请日：2014-06-12
申请人： QUALCOMM Incorporated
发明人： Philip Michael Clovis , Yi-Hung Tseng , Xuhao Huang , Sushma Chilukuri
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G06F13/1689 , G06F13/4243 , G06F13/4291 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , H03L7/07 , H03L7/0814
摘要： A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.
摘要翻译：提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

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