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1. 发明授权

US08166329B2 Circuit for facilitating computer system waking up from sleep state 失效
标题翻译：用于促进计算机系统从睡眠状态唤醒的电路
公开(公告)号：US08166329B2
公开(公告)日：2012-04-24
申请号：US12508178
申请日：2009-07-23
申请人： Qi-Jie Chen
发明人： Qi-Jie Chen
IPC分类号： G05F1/10 , G05F1/40
CPC分类号： G06F1/26
摘要： A circuit for a computer system, includes a pulse width module (PWM) module and a control circuit. The PWM module is capable of converting a first voltage to a second voltage. The first voltage is capable of decreasing slower than the second voltage to have the PWM module entering in an unwanted state when the computer system is changed from a first state to a second state. The PWM module includes a disabling pin capable of locking the PWM module when a voltage of the disabling pin is low. The control circuit includes a control pin connected to the disabling pin, a ground pin connected to ground, and a monitoring pin capable of monitoring the computer system being changed from a first state to a second state to control the control pin and the ground pin to pull the disabling pin low to lock the PWM module to prevent the PWM module from entering in the unwanted state.
摘要翻译：一种用于计算机系统的电路，包括脉冲宽度模块（PWM）模块和控制电路。 PWM模块能够将第一电压转换为第二电压。当计算机系统从第一状态改变到第二状态时，第一电压能够比第二电压慢，以使PWM模块进入不期望的状态。 PWM模块包括禁用引脚，当禁用引脚的电压低时，该引脚能够锁定PWM模块。所述控制电路包括连接到所述禁用引脚的控制引脚，连接到地的接地引脚和能够监视从第一状态改变到第二状态的计算机系统的监视引脚，以控制所述控制引脚和所述接地引脚将禁用引脚拉低，锁定PWM模块，防止PWM模块进入不需要的状态。

2. 发明申请

US20070157034A1 CIRCUIT FOR PROTECTING MOTHERBOARD 失效
标题翻译：保护母板电路
公开(公告)号：US20070157034A1
公开(公告)日：2007-07-05
申请号：US11308750
申请日：2006-04-28
申请人： Ze-Shu Ren , Qi-Jie Chen
发明人： Ze-Shu Ren , Qi-Jie Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/30
摘要： An assembly includes a circuit board (20) with a component attached thereon, a power supply (10) for providing power to the circuit board and the component separately, an ACPI chipset (65) for controlling the power supply, a protecting circuit (61) connected to the component, an I/O controller (64), and an enable circuit (62) for activating the I/O controller. The protecting circuit generates a protecting signal while the component is not connected properly to its power source. The I/O controller is responsive to the protecting signal to send a control signal to the ACPI chipset for shutting off the power supply.
摘要翻译：一种组件包括其上附着有部件的电路板（20），用于向电路板和组件单独提供电力的电源（10），用于控制电源的ACPI芯片组（65），保护电路（61）），I / O控制器（64）和用于激活I / O控制器的使能电路（62）。保护电路在组件未正确连接到其电源时产生保护信号。 I / O控制器响应于保护信号向ACPI芯片组发送控制信号以关闭电源。

3. 发明申请

US20100301908A1 CIRCUIT FOR CONTROLLING PSON SIGNAL 失效
标题翻译：控制PSON信号电路
公开(公告)号：US20100301908A1
公开(公告)日：2010-12-02
申请号：US12537658
申请日：2009-08-07
申请人： Qi-Jie Chen
发明人： Qi-Jie Chen
IPC分类号： H03L7/00
CPC分类号： G06F1/26
摘要： A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.
摘要翻译：电路包括具有PSON引脚的ATX电源连接器，时间延迟电路和稳定器电路。时间延迟电路接收到输入的PSON＃信号，然后在经过了时间延迟之后，将PSON＃输出信号发送到电源连接器的PSON引脚。稳定器电路耦合到电源连接器的PSON引脚，用于稳定输出PSON＃信号。

4. 发明授权

US07493507B2 System for protecting a motherboard while a component is not connected properly to its power source 失效
标题翻译：组件未正确连接到电源时用于保护主板的系统
公开(公告)号：US07493507B2
公开(公告)日：2009-02-17
申请号：US11308750
申请日：2006-04-28
申请人： Ze-Shu Ren , Qi-Jie Chen
发明人： Ze-Shu Ren , Qi-Jie Chen
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/30
摘要： An assembly includes a circuit board (20) with a component attached thereon, a power supply (10) for providing power to the circuit board and the component separately, an ACPI chipset (65) for controlling the power supply, a protecting circuit (61) connected to the component, an I/O controller (64), and an enable circuit (62) for activating the I/O controller. The protecting circuit generates a protecting signal while the component is not connected properly to its power source. The I/O controller is responsive to the protecting signal to send a control signal to the ACPI chipset for shutting off the power supply.
摘要翻译：一种组件包括其上附着有部件的电路板（20），用于向电路板和组件单独提供电力的电源（10），用于控制电源的ACPI芯片组（65），保护电路（61）），I / O控制器（64）和用于激活I / O控制器的使能电路（62）。保护电路在组件未正确连接到其电源时产生保护信号。 I / O控制器响应于保护信号向ACPI芯片组发送控制信号以关闭电源。

5. 发明授权

US08482324B2 Circuit for controlling PSON signal 失效
标题翻译：用于控制PSON信号的电路
公开(公告)号：US08482324B2
公开(公告)日：2013-07-09
申请号：US12537658
申请日：2009-08-07
申请人： Qi-Jie Chen
发明人： Qi-Jie Chen
IPC分类号： H03L7/00
CPC分类号： G06F1/26
摘要： A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.
摘要翻译：电路包括具有PSON引脚的ATX电源连接器，时间延迟电路和稳定器电路。时间延迟电路接收到输入的PSON＃信号，然后在经过了时间延迟之后，将PSON＃输出信号发送到电源连接器的PSON引脚。稳定器电路耦合到电源连接器的PSON引脚，用于稳定输出PSON＃信号。

6. 发明授权

US08201003B2 Circuit for preventing computer power down sequence failure 失效
标题翻译：防止电脑电源故障序列故障的电路
公开(公告)号：US08201003B2
公开(公告)日：2012-06-12
申请号：US12556786
申请日：2009-09-10
申请人： Qi-Jie Chen
发明人： Qi-Jie Chen
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F11/30
CPC分类号： H03K17/28 , G06F1/3203
摘要： A circuit for confirming a correct computer power down sequence includes a Southbridge chip, a first switching transistor circuit, and a second switching transistor circuit. The first switching transistor circuit receives a power good signal. The second switching transistor circuit receives a S3 sleep signal. The first and second switching transistor circuits have a common output node coupled to the Southbridge chip. During a computer power down sequence, the S3 sleep signal is set from high to low before than the power good signal, and the S3 sleep signal is active and fed to the Southbridge chip, thereby quickly providing a low level power good signal to the Southbridge chip and confirming the power down sequence is correct.
摘要翻译：用于确认正确的计算机断电序列的电路包括南桥芯片，第一开关晶体管电路和第二开关晶体管电路。第一开关晶体管电路接收电力良好信号。第二开关晶体管电路接收S3睡眠信号。第一和第二开关晶体管电路具有耦合到南桥芯片的公共输出节点。在计算机断电序列期间，S3休眠信号从电源良好信号之前的高电平设置为低电平，S3睡眠信号被激活并馈送到南桥芯片，从而快速向南桥提供低电平电力良好信号芯片并确认掉电顺序是正确的。

7. 发明授权

US08200997B2 Computer wake up circuit includes a switch configured to prevent a control signals from an I/O controller being transmitted to south-bridge 失效
标题翻译：计算机唤醒电路包括配置为防止来自I / O控制器的控制信号被传送到南桥的开关
公开(公告)号：US08200997B2
公开(公告)日：2012-06-12
申请号：US12548063
申请日：2009-08-26
申请人： Qi-Jie Chen
发明人： Qi-Jie Chen
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3215
摘要： A computer wake up circuit includes a first control circuit and a second control circuit. The first control circuit has an input terminal configured to receive a first control signal from a first serial device, and an output terminal coupled to a south bridge which is capable of waking up a computer. The second control circuit has an input terminal respectively coupled to a second serial device and an I/O controller, and an output terminal coupled to the south bridge. The second control circuit receives a second control signal from the second serial device. The first and second control circuits respectively outputs a wake up signal to the south bridge to wake up the computer according to the control signals. The I/O controller communicates with the second serial device through the second control circuit, and outputs other control signals to control operations of the second serial device.
摘要翻译：计算机唤醒电路包括第一控制电路和第二控制电路。第一控制电路具有被配置为从第一串行设备接收第一控制信号的输入端子和耦合到能够唤醒计算机的南桥的输出端子。第二控制电路具有分别耦合到第二串行设备和I / O控制器的输入端子以及耦合到南桥的输出端子。第二控制电路从第二串行装置接收第二控制信号。第一和第二控制电路分别向南桥输出唤醒信号，以根据控制信号唤醒计算机。 I / O控制器通过第二控制电路与第二串行设备通信，并输出其他控制信号以控制第二串行设备的操作。

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