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1. 发明授权

US10770802B2 Antenna on a device assembly 有权
公开(公告)号：US10770802B2
公开(公告)日：2020-09-08
申请号：US14933552
申请日：2015-11-05
申请人： RF Micro Devices, Inc.
发明人： Alexander Wayne Hietala , Julio C. Costa
IPC分类号： H01Q1/38 , H01Q19/10 , H01Q1/24 , H01L23/66 , H01L23/552 , H01Q21/06 , H01Q1/40 , H01Q9/04 , H01L23/522 , H01Q1/22 , H01L23/00
摘要： Aspects disclosed in the detailed description include an antenna on a device assembly. A device assembly includes a silicon device layer having at least one antenna. The device assembly also includes a polymer substrate that is formed with insulating material that does not interfere with the at least one antenna in the silicon device layer. As a result, it is unnecessary to shield the at least one antenna from the polymer substrate, thus allowing radio frequency (RF) signals radiating from the at least one antenna to pass through the polymer substrate.

2. 发明授权

US09519612B2 Serial bus buffer with noise reduction 有权
标题翻译：具有降噪功能的串行总线缓冲器
公开(公告)号：US09519612B2
公开(公告)日：2016-12-13
申请号：US14160900
申请日：2014-01-22
申请人： RF Micro Devices, Inc.
发明人： Alexander Wayne Hietala , Christopher Truong Ngo , Eric K. Bolton
IPC分类号： G06F13/24 , G06F13/42
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.
摘要翻译：公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与缓冲总线。主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。

3. 发明授权

US09337787B2 Power amplifier with improved low bias mode linearity 有权
标题翻译：功率放大器具有改进的低偏置模式线性度
公开(公告)号：US09337787B2
公开(公告)日：2016-05-10
申请号：US14304149
申请日：2014-06-13
申请人： RF Micro Devices, Inc.
发明人： Derek Schooley , Alexander Wayne Hietala
IPC分类号： H03G3/30 , H03F3/21 , H03F1/02 , H03F3/191
CPC分类号： H03F3/21 , H03F1/0261 , H03F3/191 , H03F2200/18 , H03F2200/27 , H03F2200/451 , H03G3/30
摘要： Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.
摘要翻译：功率放大器电路包括功率放大器，其包括输入节点和输出节点，偏置电路，可选阻抗网络和输入电容器。输入电容器耦合到功率放大器的输入节点。偏置电路通过可选择的阻抗网络耦合到功率放大器的输入节点。功率放大器可在低功率工作模式和高功率工作模式下工作。在低功率操作模式中，偏置电路将第一偏置电流传送到功率放大器的输入节点，并且选择可选阻抗的第一阻抗级别。在高功率操作模式中，偏置电路将第二偏置电流传递到功率放大器的输入节点，并且选择可选择阻抗的第二阻抗水平。

4. 发明申请

US20140111275A1 EFFICIENT POWER TRANSFER POWER AMPLIFIER (PA) ARCHITECTURE 有权
标题翻译：高效的功率放大器（PA）架构
公开(公告)号：US20140111275A1
公开(公告)日：2014-04-24
申请号：US14056135
申请日：2013-10-17
申请人： RF Micro Devices, Inc.
发明人： Nadim Khlat , Alexander Wayne Hietala
IPC分类号： H03F1/56 , H03F3/68 , H03F3/20
CPC分类号： H03F1/56 , H03F3/20 , H03F3/24 , H03F3/68 , H03F2200/387 , H03F2200/537 , H03F2200/541
摘要： An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.
摘要翻译：公开了一种有效的功率传输功率放大器（PA）架构，其包括第一PA，耦合到第一PA的第一阻抗变换网络（ITN），第二PA和耦合到第二PA的第二ITN。一种具有多个负载输出以及耦合到第一ITN的第一阻抗输出的第一开关输入和耦合到第一ITN的第二阻抗输出的第二开关输入的开关网络，耦合到第三阻抗的第三开关输入第二ITN的输出和耦合到第二ITN的第四阻抗输出的第四开关输入。控制系统适于控制开关网络以在第一，第二，第三和第四开关输入端切换信号，使得信号中的选择信号将具有匹配阻抗的路径传递到耦合到多个负载输出的负载。

5. 发明授权

US10579580B2 Start of sequence detection for one wire bus 有权
公开(公告)号：US10579580B2
公开(公告)日：2020-03-03
申请号：US14659292
申请日：2015-03-16
申请人： RF Micro Devices, Inc.
发明人： Christopher Truong Ngo , Alexander Wayne Hietala
IPC分类号： G06F13/00 , G06F13/42 , G06F13/364 , G06F13/40 , G06F13/362
摘要： The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

6. 发明授权

US10282269B2 Read technique for a bus interface system 有权
公开(公告)号：US10282269B2
公开(公告)日：2019-05-07
申请号：US14659328
申请日：2015-03-16
申请人： RF Micro Devices, Inc.
发明人： Christopher Truong Ngo , Alexander Wayne Hietala
IPC分类号： G06F11/30 , H04L1/16 , H04L7/027 , H04L1/00 , G06F1/10 , G06F11/00 , G06F13/362 , G06F11/22 , G06F1/26
摘要： Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

7. 发明授权

US10049026B2 Group write technique for a bus interface system 有权
公开(公告)号：US10049026B2
公开(公告)日：2018-08-14
申请号：US14659379
申请日：2015-03-16
申请人： RF Micro Devices, Inc.
发明人： Christopher Truong Ngo , Alexander Wayne Hietala
IPC分类号： G06F11/30 , G06F1/26 , G06F1/10 , G06F11/22 , G06F11/16 , G06F11/10
摘要： Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

8. 发明授权

US09711999B2 Antenna array calibration for wireless charging 有权
公开(公告)号：US09711999B2
公开(公告)日：2017-07-18
申请号：US14851642
申请日：2015-09-11
申请人： RF Micro Devices, Inc.
发明人： Alexander Wayne Hietala , Nadim Khlat
IPC分类号： H02J7/00 , H02J50/10 , H02J50/80 , H02J50/23
CPC分类号： H02J50/10 , H02J50/23 , H02J50/80
摘要： Antenna array calibration for wireless charging is disclosed. A wireless charging system is provided and configured to calibrate antenna elements in a wireless charging station based on a feedback signal provided by a wireless charging device. The antenna elements in the wireless charging station transmit wireless radio frequency (RF) charging signals to the wireless charging device. The wireless charging device provides the feedback signal to the wireless charging station to indicate total RF power in the wireless RF charging signals. The wireless charging station is configured to adjust transmitter phases associated with the antenna elements based on the feedback signal until the total RF power in the wireless RF charging signals is maximized. By calibrating the antenna elements based on the feedback signal, it is possible to achieve phase coherency among the antenna elements without requiring factory calibration.

9. 发明申请

US20150193298A1 WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM 审中-公开
标题翻译：用于总线接口系统的写入技术
公开(公告)号：US20150193298A1
公开(公告)日：2015-07-09
申请号：US14659355
申请日：2015-03-16
申请人： RF Micro Devices, Inc.
发明人： Christopher Truong Ngo , Alexander Wayne Hietala
IPC分类号： G06F11/08 , G06F11/30 , G06F11/22
摘要： Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.
摘要翻译：公开了总线接口系统的实施例。在一个实施例中，总线接口系统包括主总线控制器和耦合到总线的从总线控制器。主总线控制器被配置为沿着表示有效载荷段的总线产生第一组数据脉冲。从总线控制器被配置为将表示有效载荷段的第一组数据脉冲解码为经解码的有效载荷段。从属总线控制器然后被配置为对解码的有效载荷段执行第一错误检查。此外，从总线控制器被配置为沿着总线产生确认信号，使得确认信号指示经解码的有效载荷段通过第一错误检查。以这种方式，主总线控制器可以确定从总线控制器接收到有效载荷段的准确副本。

10. 发明申请

US20150192974A1 POWER MANAGEMENT SYSTEM FOR A BUS INTERFACE SYSTEM 审中-公开
标题翻译：用于总线接口系统的电源管理系统
公开(公告)号：US20150192974A1
公开(公告)日：2015-07-09
申请号：US14659371
申请日：2015-03-16
申请人： RF Micro Devices, Inc.
发明人： Christopher Truong Ngo , Alexander Wayne Hietala , Christian Rye Iversen , Ruediger Bauder
IPC分类号： G06F1/26 , G06F13/40 , G06F13/364 , G06F1/32
摘要： Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.
摘要翻译：公开了总线接口系统的实施例。在一个实施例中，总线接口系统包括总线控制器和沿总线耦合的从总线控制器。主总线控制器被配置为产生由总线控制器沿总线接收的输入数据信号。从总线控制器包括被配置为将来自主总线控制器的输入数据信号转换成电源电压的功率转换电路。通过提供电源转换电路，从总线控制器使用输入数据信号供电，而不需要额外的总线来将电源电压传送到从总线控制器。

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