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1. 发明授权

US07921275B2 Method for enabling direct prefetching of data during asychronous memory move operation 失效
标题翻译：用于在异步存储器移动操作期间直接预取数据的方法
公开(公告)号：US07921275B2
公开(公告)日：2011-04-05
申请号：US12024598
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30087 , G06F9/3017 , G06F9/30185 , G06F9/3834 , G06F9/3877
摘要： While an asynchronous memory move (AMM) operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers cache injection by the AMM mover of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache, the next cache lines in the sequence of data to the L2 cache, and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller places moved data into only a subset of the available cache lines of the upper level cache.
摘要翻译：当异步存储器移动（AMM）操作正在进行时，来自源有效地址或目的地有效地址的数据的预取请求触发AMM移动器对来自物理存储器中移动的数据流的相关数据的高速缓存注入。存储器控制器将第一预取行转发到预取引擎和L1高速缓存，将数据序列中的下一个高速缓存行转发到L2高速缓存，以及将后续的一组高速缓存行转发到L3高速缓存。存储器控制器然后将剩余的数据转发到目的地存储器位置。通过缓存高速缓存中的数据流，而不是将所有移动的数据放在内存中，可以快速访问预取数据。此外，存储器控制器将移动的数据仅放置在高级缓存的可用高速缓存行的子集中。

2. 发明申请

US20090198963A1 COMPLETION OF ASYNCHRONOUS MEMORY MOVE IN THE PRESENCE OF A BARRIER OPERATION 失效
标题翻译：在障碍物操作中完成异步记忆移动
公开(公告)号：US20090198963A1
公开(公告)日：2009-08-06
申请号：US12024513
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F9/30
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3834 , G06F9/3885 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.
摘要翻译：数据处理系统中的方法，通过该方法，处理器执行异步存储器移动（AMM）存储（ST）指令以与正在进行的（未完成）先前发布的屏障操作并行地完成对应的AMM操作。执行屏障操作（或SYNC指令）后，在系统结构上完成屏障操作或SYNC之前，处理器接收AMM ST指令。处理器继续执行AMM ST指令，其在虚拟地址空间中执行移动，然后触发AMM操作的生成。无障碍操作继续进行，与处理器无关，AMM操作继续进行。处理器停止所有其他存储器访问请求的进一步执行，排除在屏障操作之后但在屏障操作完成之前接收的AMM ST指令。

3. 发明授权

US08327101B2 Cache management during asynchronous memory move operations 有权
标题翻译：异步存储器移动操作期间的缓存管理
公开(公告)号：US08327101B2
公开(公告)日：2012-12-04
申请号：US12024526
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F12/0815 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3877 , G06F12/10
摘要： A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
摘要翻译：数据处理系统包括用于完成异步存储器移动（AMM）操作的机制，其中处理器接收AMM ST指令并处理虚拟地址空间中的数据的处理器级移动，然后异步存储器移动器完成物理移动实际地址空间（内存）中的数据。 AMM ST指令的状态/控制字段在完成AMM操作时包括对低级缓存的请求处理的指示。当状态/控制字段指示应该执行至少一个缓存的更新时，异步存储器移动器自动将数据的副本从数据移动转发到较低级的高速缓存，并触发高速缓存的一致性状态的更新其中放置数据副本的行。

4. 发明授权

US08095758B2 Fully asynchronous memory mover 失效
标题翻译：全异步内存移动器
公开(公告)号：US08095758B2
公开(公告)日：2012-01-10
申请号：US12024613
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F12/04
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.
摘要翻译：数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。异步存储器移动器具有相关的片外转换机制。因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。

5. 发明授权

US07937570B2 Termination of in-flight asynchronous memory move 有权
标题翻译：终止飞行中的异步内存移动
公开(公告)号：US07937570B2
公开(公告)日：2011-05-03
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: an asynchronous memory mover (AMM) store (ST) instruction that initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and a LD CMP instruction for checking a status of an AMM operation.
摘要翻译：数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：异步存储器移动器（AMM）存储（ST）指令，其启动异步存储器移动操作，其从具有第一存储器位置的第一存储器位置移动数据，具有第二实际地址的第二存储器位置的第一实际地址：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA还提供用于在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及用于检查AMM操作的状态的LD CMP指令。

6. 发明申请

US20090198975A1 TERMINATION OF IN-FLIGHT ASYNCHRONOUS MEMORY MOVE 有权
标题翻译：飞行异常记忆移动的终止
公开(公告)号：US20090198975A1
公开(公告)日：2009-08-06
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: (1) an asynchronous memory mover (AMM) store (ST) instruction initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides (2) an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and (3) a LD CMP instruction for checking a status of an AMM operation.
摘要翻译：数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：（1）异步存储器移动器（AMM）存储器（ST）指令发起异步存储器移动操作，其将数据从第一存储器具有通过以下方式具有第二实际地址的具有第一实际地址的位置：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA进一步提供（2）在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及（3）用于检查AMM操作状态的LD CMP指令。

7. 发明申请

US20090198939A1 LAUNCHING MULTIPLE CONCURRENT MEMORY MOVES VIA A FULLY ASYNCHRONOOUS MEMORY MOVER 失效
标题翻译：启动多个同时存储器通过充分的异步存储器移动
公开(公告)号：US20090198939A1
公开(公告)日：2009-08-06
申请号：US12024690
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3851 , G06F12/10
摘要： A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist.
摘要翻译：数据处理系统具有异步存储器移动器，其包括用于存储用于生成一个或多个异步存储器移动（AMM）操作的寻址和控制参数的多组寄存器。存储器移动器检测来自处理器的第一组寄存器中的第一组参数的接收。处理器在虚拟地址空间中启动数据移动后，使用源有效地址和目标有效地址，处理器转发参数。存储器移动器响应于通过生成和启动第一异步存储器移动（AMM）操作来接收第一组参数。当存储器移动器在第一个AMM操作完成之前在第二组寄存器中接收到第二组参数时，如果不存在地址冲突，则存储器移动器生成并与第一个AMM操作同时启动第二个AMM操作。

8. 发明申请

US20090198908A1 METHOD FOR ENABLING DIRECT PREFETCHING OF DATA DURING ASYCHRONOUS MEMORY MOVE OPERATION 失效
标题翻译：用于在异步存储器运行期间实现数据的直接预先提取的方法
公开(公告)号：US20090198908A1
公开(公告)日：2009-08-06
申请号：US12024598
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： RAVI K. ARIMILLI , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30087 , G06F9/3017 , G06F9/30185 , G06F9/3834 , G06F9/3877
摘要： While an AMM operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers a cache injection by the AMM mover (or memory controller) of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache. The memory controller also forwards the next cache lines in the sequence of data to the L2 cache and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller does not overrun the upper caches, by placing moved data into only a subset of the available cache lines of the upper level cache.
摘要翻译：当AMM操作正在进行时，来自源有效地址或目的地有效地址的数据的预取请求触发AMM移动器（或存储器控制器）从在物理存储器中移动的数据流中的相关数据的高速缓存注入。存储器控制器将第一预取行转发到预取引擎和L1缓存。存储器控制器还将数据序列中的下一个高速缓存行转发到L2高速缓存以及随后的一组高速缓存行到L3高速缓存。存储器控制器然后将剩余的数据转发到目的地存储器位置。通过缓存高速缓存中的数据流，而不是将所有移动的数据放在内存中，可以快速访问预取数据。此外，通过将移动的数据仅放置在高级缓存的可用高速缓存行的一部分中，存储器控制器不会超过上部高速缓存。

9. 发明授权

US08015380B2 Launching multiple concurrent memory moves via a fully asynchronoous memory mover 失效
标题翻译：通过完全异步的内存移动器启动多个并发内存移动
公开(公告)号：US08015380B2
公开(公告)日：2011-09-06
申请号：US12024690
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3851 , G06F12/10
摘要： A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist.
摘要翻译：数据处理系统具有异步存储器移动器，其包括用于存储用于生成一个或多个异步存储器移动（AMM）操作的寻址和控制参数的多组寄存器。存储器移动器检测来自处理器的第一组寄存器中的第一组参数的接收。处理器在虚拟地址空间中启动数据移动后，使用源有效地址和目标有效地址，处理器转发参数。存储器移动器响应于通过生成和启动第一异步存储器移动（AMM）操作来接收第一组参数。当存储器移动器在第一个AMM操作完成之前在第二组寄存器中接收到第二组参数时，如果不存在地址冲突，则存储器移动器生成并与第一个AMM操作同时启动第二个AMM操作。

10. 发明申请

US20090198936A1 REPORTING OF PARTIALLY PERFORMED MEMORY MOVE 有权
标题翻译：报告部分执行记忆移动
公开(公告)号：US20090198936A1
公开(公告)日：2009-08-06
申请号：US12024504
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/30043 , G06F12/0831 , G06F12/0862 , G06F12/1027
摘要： A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received.
摘要翻译：在数据处理系统中执行的方法启动异步存储器移动（AMM）操作，由此处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并将AMM操作的参数转发到异步存储器用于完成数据从第一存储器位置到第二存储器位置的物理移动的移动器逻辑。处理器执行第二操作，其检查数据移动完成的状态，并返回指示状态的通知。该通知表示状态，其中包括：数据移动进行中的一个; 数据移动完成; 数据移动部分完成; 无法执行数据移动; 以及出现翻译后备缓冲区无效条目（TLBIE）操作。处理器响应于收到的通知发起一个或多个动作。

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