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1. 发明授权

US10340193B2 Fin field effect transistor and manufacturing method thereof 有权
公开(公告)号：US10340193B2
公开(公告)日：2019-07-02
申请号：US15432626
申请日：2017-02-14
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Ta-Hsun Yeh , Cheng-Wei Luo , Hsiao-Tsung Yen , Yuh-Sheng Jean
IPC分类号： H01L29/06 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/762
摘要： A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure. The isolation structure disposed on the substrate to isolate the gate-stacked structure from the substrate has different thicknesses in different portions.

2. 发明授权

US10269733B2 Integrated circuit device 有权
公开(公告)号：US10269733B2
公开(公告)日：2019-04-23
申请号：US15435498
申请日：2017-02-17
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01L23/00 , H01L23/66 , H01L23/495
摘要： The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first ground line includes a first pad, a second pad and a first bonding wire that is a bond wire structure connecting the first pad and the second pad. The first signal line includes a third pad, a fourth pad and a second bonding wire that is a bond wire structure connecting the third pad and the fourth pad.

3. 发明申请

US20170236791A1 INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：US20170236791A1
公开(公告)日：2017-08-17
申请号：US15435498
申请日：2017-02-17
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01L23/66 , H01L23/00 , H01L23/495
CPC分类号： H01L23/66 , H01L23/4952 , H01L24/09 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6627 , H01L2224/0912 , H01L2224/45015 , H01L2224/45111 , H01L2224/45124 , H01L2224/45147 , H01L2224/4813 , H01L2224/4912 , H01L2924/00014 , H01L2924/20751 , H01L2924/20752
摘要： The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first ground line includes a first pad, a second pad and a first bonding wire that is a bond wire structure connecting the first pad and the second pad. The first signal line includes a third pad, a fourth pad and a second bonding wire that is a bond wire structure connecting the third pad and the fourth pad.

4. 发明申请

US20160035887A1 SEMICONDUCTOR DEVICE AND MULTIPLE GATE FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和多栅极场效应晶体管
公开(公告)号：US20160035887A1
公开(公告)日：2016-02-04
申请号：US14814487
申请日：2015-07-30
申请人： Realtek Semiconductor Corp.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/7831 , H01L29/4236 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/785
摘要： The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.
摘要翻译：本发明提供一种半导体器件，其包括基板，第一栅极电极，第二栅极电极，源极区域和漏极区域，其中第一栅极电极和第二栅极电极分别嵌入基板; 源极区域形成在衬底中，并且源区域的至少一部分设置在第一栅电极和第二栅电极之间; 并且所述漏极区域形成在所述衬底中，并且所述漏极区域的至少一部分设置在所述第一栅电极和所述第二栅电极之间。

5. 发明授权

US10186364B2 Electronic device with two planar inductors 有权
公开(公告)号：US10186364B2
公开(公告)日：2019-01-22
申请号：US14722167
申请日：2015-05-27
申请人： Realtek Semiconductor Corp.
发明人： Hsiao-Tsung Yen , Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F27/28 , H01F17/00 , H01F27/34
摘要： An electronic device includes a first planar inductor and a second planar inductor. The first planar inductor includes at least a first ring structure and a second ring structure interconnected electrically for generating a first magnetic field having a first direction and a second magnetic field having a second direction respectively, wherein the first direction is different from the second direction. The second planar inductor includes at least a third ring structure and a fourth ring structure interconnected electrically for generating a third magnetic field having a third direction and a fourth magnetic field having a fourth direction respectively, wherein the third direction is different from the fourth direction. The first ring structure at least partially overlaps the third ring structure to form a first overlap region, and the second ring structure at least partially overlaps the fourth ring structure to form a second overlap region.

6. 发明申请

US20150364243A1 ELECTRONIC DEVICE WITH TWO PLANAR INDUCTORS 审中-公开
标题翻译：具有两个平面电感器的电子设备
公开(公告)号：US20150364243A1
公开(公告)日：2015-12-17
申请号：US14722167
申请日：2015-05-27
申请人： Realtek Semiconductor Corp.
发明人： Hsiao-Tsung Yen , Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F27/28
CPC分类号： H01F27/2804 , H01F17/0033 , H01F27/346 , H01F2017/0073 , H01F2027/2809
摘要： An electronic device includes a first planar inductor and a second planar inductor. The first planar inductor includes at least a first ring structure and a second ring structure interconnected electrically for generating a first magnetic field having a first direction and a second magnetic field having a second direction respectively, wherein the first direction is different from the second direction. The second planar inductor includes at least a third ring structure and a fourth ring structure interconnected electrically for generating a third magnetic field having a third direction and a fourth magnetic field having a fourth direction respectively, wherein the third direction is different from the fourth direction. The first ring structure at least partially overlaps the third ring structure to form a first overlap region, and the second ring structure at least partially overlaps the fourth ring structure to form a second overlap region.
摘要翻译：电子设备包括第一平面电感器和第二平面电感器。第一平面电感器包括至少第一环形结构和第二环形结构，其电连接以产生具有第一方向的第一磁场和分别具有第二方向的第二磁场，其中第一方向与第二方向不同。第二平面电感器包括至少第三环形结构和第四环形结构，电连接用于分别产生具有第三方向的第三磁场和具有第四方向的第四磁场，其中第三方向与第四方向不同。第一环结构至少部分地与第三环结构重叠以形成第一重叠区域，并且第二环结构至少部分地与第四环结构重叠以形成第二重叠区域。

7. 发明申请

US20150310981A1 INTEGRATED TRANSFORMER 有权
标题翻译：集成变压器
公开(公告)号：US20150310981A1
公开(公告)日：2015-10-29
申请号：US14719297
申请日：2015-05-21
申请人： Realtek Semiconductor Corp.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F27/28 , H01F38/14
CPC分类号： H01F27/2804 , H01F5/00 , H01F38/14 , H01F2027/2809
摘要： An integrated transformer includes a primary inductor and a secondary inductor wherein the primary inductor includes a B turns spiral winding formed by a first metal layer and an A turns winding formed by a second metal layer, wherein the A turns winding formed by the second metal layer and the innermost turns of the B turns spiral winding formed by the first metal layer are substantially overlapped; and the secondary inductor includes a C turns winding at least formed by the second metal layer, wherein the C turns winding formed by the second metal layer of the secondary inductor and a portion of the winding formed by the first metal layer of the primary inductor are substantially overlapped, wherein A is not bigger than B, and A is not bigger than C.
摘要翻译：集成变压器包括初级电感器和次级电感器，其中初级电感器包括由第一金属层形成的B匝螺旋绕组和由第二金属层形成的A匝绕组，其中A匝绕第二金属层形成的绕组并且由第一金属层形成的B的最内圈匝大致重叠; 并且次级电感器包括至少由第二金属层形成的C匝绕组，其中C匝绕由次级电感器的第二金属层形成的绕组和由初级电感器的第一金属层形成的绕组的一部分是基本上重叠，其中A不大于B，A不大于C.

8. 发明授权

US10943730B2 Single-ended inductor 有权
公开(公告)号：US10943730B2
公开(公告)日：2021-03-09
申请号：US15462344
申请日：2017-03-17
申请人： Realtek Semiconductor Corp.
发明人： Cheng Wei Luo , Hsiao-Tsung Yen , Ta-Hsun Yeh , Yuh-Sheng Jean
IPC分类号： H01F5/04 , H01F27/34 , H01F17/00 , H01F27/28
摘要： A single-ended inductor comprises a first partial coil wound in a first direction; and a second partial coil wound in a second direction and adjoined the first partial coil; wherein, the second direction is opposite to the first direction to reduce the coupling of single-ended inductors and peripheral lines and reduce signal interference.

9. 发明申请

US20150348702A1 PARAMETER-VARIABLE DEVICE, VARIABLE INDUCTOR AND DEVICE HAVING THE VARIABLE INDUCTOR 有权
标题翻译：参数可变器件，可变电感器和具有可变电感器的器件
公开(公告)号：US20150348702A1
公开(公告)日：2015-12-03
申请号：US14505812
申请日：2014-10-03
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F29/02 , H01F27/29
CPC分类号： H01F21/12 , H01F27/32 , H01F2021/125
摘要： A device having a variable inductor includes an inductor having an inductance, a first conductor having a first grounding property, and a second conductor having a second grounding property. The device further includes a first single-mesh structure including a first grid. The first grid includes a first conducting wire electrically connected to the first conductor, and a second conducting wire electrically connected to the first conducting wire and the first conductor, wherein the first conducting wire, the second conducting wire and the first conductor are configured to form a first loop corresponding to the inductor for tuning the inductance. The first single-mesh structure further includes a second grid. The second grid includes a third conducting wire electrically connected to the first conducting wire and the second conductor, and a fourth conducting wire electrically connected to the third conducting wire and the second conductor, wherein the third conducting wire, the fourth conducting wire and the second conductor are configured to form a second loop corresponding to the inductor for tuning the inductance.
摘要翻译：具有可变电感器的装置包括具有电感的电感器，具有第一接地特性的第一导体和具有第二接地特性的第二导体。该装置还包括包括第一格栅的第一单网结构。第一栅格包括电连接到第一导体的第一导线和电连接到第一导线和第一导体的第二导线，其中第一导线，第二导线和第一导体被配置成形成对应于用于调谐电感的电感器的第一回路。第一单网结构还包括第二网格。第二栅格包括电连接到第一导线和第二导体的第三导线和电连接到第三导线和第二导体的第四导线，其中第三导线，第四导线和第二导线导体被配置为形成对应于电感器的第二回路以调谐电感。

10. 发明授权

US09935196B2 Semiconductor device and multiple gate field effect transistor 有权
公开(公告)号：US09935196B2
公开(公告)日：2018-04-03
申请号：US14814487
申请日：2015-07-30
申请人： Realtek Semiconductor Corp.
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7831 , H01L29/4236 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/785
摘要： The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.

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