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1. 发明授权

US09612909B2 Computer system 有权
公开(公告)号：US09612909B2
公开(公告)日：2017-04-04
申请号：US14887662
申请日：2015-10-20
申请人： Renesas Electronics Corporation
发明人： Hirotaka Motai , Yasuhiro Tawara , Koji Adachi , Hitoshi Suzuki
IPC分类号： G06F9/455 , G06F11/14 , G06F11/07 , G06F9/44 , G06F11/30
CPC分类号： G06F11/0772 , G06F9/30101 , G06F9/3836 , G06F9/4405 , G06F9/455 , G06F9/45533 , G06F11/0712 , G06F11/0745 , G06F11/0751 , G06F11/0793 , G06F11/1438 , G06F11/1484 , G06F11/3027 , G06F13/24 , G06F13/4027 , G06F13/4068 , G06F2201/84
摘要： A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

2. 发明申请

US20160041883A1 COMPUTER SYSTEM 有权
标题翻译：电脑系统
公开(公告)号：US20160041883A1
公开(公告)日：2016-02-11
申请号：US14887662
申请日：2015-10-20
申请人： Renesas Electronics Corporation
发明人： Hirotaka Motai , Yasuhiro Tawara , Koji Adachi , Hitoshi Suzuki
IPC分类号： G06F11/14 , G06F11/30 , G06F9/455 , G06F11/07 , G06F9/44
CPC分类号： G06F11/0772 , G06F9/30101 , G06F9/3836 , G06F9/4405 , G06F9/455 , G06F9/45533 , G06F11/0712 , G06F11/0745 , G06F11/0751 , G06F11/0793 , G06F11/1438 , G06F11/1484 , G06F11/3027 , G06F13/24 , G06F13/4027 , G06F13/4068 , G06F2201/84
摘要： A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.
摘要翻译：计算机系统包括用于通知总线错误发生的中断控制器和多线程处理器。多线程处理器包括调度寄存器，该调度寄存器确定执行多个虚拟CPU并且存储要执行的虚拟CPU的数据的顺序，以及虚拟CPU执行部，其根据由调度寄存器确定的顺序执行虚拟CPU。虚拟CPU操作不同的操作系统（OS），并且包括操作管理操作系统以管理其他操作系统的第一个虚拟CPU。当通知总线错误发生时，虚拟CPU执行部分仅操作第一虚拟CPU，而不管安排在调度寄存器中的执行顺序如何。第一个虚拟CPU重新初始化发生错误的总线。

3. 发明授权

US09223573B2 Data processing device and method of controlling the same 有权
公开(公告)号：US09223573B2
公开(公告)日：2015-12-29
申请号：US14596972
申请日：2015-01-14
申请人： Renesas Electronics Corporation
发明人： Hitoshi Suzuki , Yukihiko Akaike
IPC分类号： G06F9/30 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/30058 , G06F9/461 , G06F9/4825 , G06F9/4856 , G06F11/1435 , G06F11/1451 , G06F13/24
摘要： A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

4. 发明授权

US10402305B2 Computer and compiling method 有权
公开(公告)号：US10402305B2
公开(公告)日：2019-09-03
申请号：US14469837
申请日：2014-08-27
申请人： Renesas Electronics Corporation
发明人： Tsuyoshi Nagao , Shuji Satoh , Hitoshi Suzuki
IPC分类号： G06F11/00 , G06F11/36 , G06F9/30
摘要： To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

5. 发明授权

US10243568B2 Semiconductor device, control system, and synchronization method 有权
公开(公告)号：US10243568B2
公开(公告)日：2019-03-26
申请号：US15797033
申请日：2017-10-30
申请人： Renesas Electronics Corporation
发明人： Hiromichi Yamada , Akihiro Yamate , Hitoshi Suzuki , Yoichi Yuyama , Teppei Hirotsu
IPC分类号： H03K21/40 , H03K21/38
摘要： In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2, a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is set, a comparison circuit 5 configured to compare the count value in the counter 3 with the set value in the periodic register 4, a match flag register 6 in which a predetermined value is set when the count value coincides with the set value, a match output terminal 7 configured to output the value in the match flag register 6 from the own semiconductor device, a match input terminal 8 to which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counter 3 and the match flag register 6 when both the value in the match flag register 6 of the own semiconductor device and the value input to the match input terminal 8 become a predetermined value.

6. 发明申请

US20170177431A1 COMPUTER SYSTEM 审中-公开
公开(公告)号：US20170177431A1
公开(公告)日：2017-06-22
申请号：US15450197
申请日：2017-03-06
申请人： Renesas Electronics Corporation
发明人： Hirotaka Motai , Yasuhiro Tawara , Koji Adachi , Hitoshi Suzuki
IPC分类号： G06F11/07 , G06F9/30 , G06F9/38 , G06F13/40 , G06F13/24
CPC分类号： G06F11/0772 , G06F9/30101 , G06F9/3836 , G06F9/4405 , G06F9/455 , G06F9/45533 , G06F11/0712 , G06F11/0745 , G06F11/0751 , G06F11/0793 , G06F11/1438 , G06F11/1484 , G06F11/3027 , G06F13/24 , G06F13/4027 , G06F13/4068 , G06F2201/84
摘要： A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

7. 发明申请

US20150212950A1 MICROCOMPUTER AND METHOD FOR CONTROLLING MEMORY ACCESS 有权
标题翻译：用于控制存储器访问的微型计算机和方法
公开(公告)号：US20150212950A1
公开(公告)日：2015-07-30
申请号：US14678454
申请日：2015-04-03
申请人： Renesas Electronics Corporation
发明人： Rika Ono , Hitoshi Suzuki
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/14 , G06F12/1441 , G06F12/1491 , G06F2212/1052
摘要： A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.
摘要翻译：一种微型计算机，包括CPU，多个保护信息存储器，被配置为通过CPU执行的程序将存储器保护信息指定到存储器空间，所述存储器保护信息由CPU执行的程序存储到存储器空间;存储器访问控制装置，以根据存储器保护信息允许来自CPU的存储器访问请求;以及复位装置，被配置为根据从CPU输出的重置请求向多个保护信息存储器输出复位信号，根据由CPU执行的程序的切换， CPU。根据来自第一存储器保护状态的复位信号，将多个保护信息存储器中的每一个设置为第二存储器保护状态。

8. 发明授权

US09003148B2 Microcomputer and method for controlling memory access 有权
标题翻译：用于控制存储器访问的微机和方法
公开(公告)号：US09003148B2
公开(公告)日：2015-04-07
申请号：US13665639
申请日：2012-10-31
申请人： Renesas Electronics Corporation
发明人： Rika Ono , Hitoshi Suzuki
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F12/145 , G06F12/14 , G06F12/1441 , G06F12/1491 , G06F2212/1052
摘要： A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or a prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU to a switching of programs executed by the CPU, the reset request signal being based on a state of execution of the program by the CPU. The reset apparatus sets all valid bit storing fields of a plurality of protection setting registers of the protection information storage to invalid state in response to the reset request signal output by the CPU.
摘要翻译：微型计算机包括CPU，保护信息存储器，被配置为通过CPU执行的程序将存储器保护信息指定给存储器空间，存储器访问控制装置被配置为确定是否允许根据存储器保护信息从CPU获取存储器访问请求;以及复位装置，被配置为根据从CPU输出的复位请求信号使存储在保护信息存储器中的存储器保护信息无效，CPU执行的程序的切换，复位请求信号基于CPU执行程序的状态。复位装置响应于CPU输出的复位请求信号，将保护信息存储器的多个保护设置寄存器的所有有效位存储区域设置为无效状态。

9. 发明申请

US20130132694A1 MICROCOMPUTER AND METHOD FOR CONTROLLING MEMORY ACCESS 有权
标题翻译：用于控制存储器访问的微型计算机和方法
公开(公告)号：US20130132694A1
公开(公告)日：2013-05-23
申请号：US13665639
申请日：2012-10-31
申请人： Renesas Electronics Corporation
发明人： Rika Ono , Hitoshi Suzuki
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/14 , G06F12/1441 , G06F12/1491 , G06F2212/1052
摘要： A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or a prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU to a switching of programs executed by the CPU, the reset request signal being based on a state of execution of the program by the CPU. The reset apparatus sets all valid bit storing fields of a plurality of protection setting registers of the protection information storage to invalid state in response to the reset request signal output by the CPU.
摘要翻译：微型计算机包括CPU，保护信息存储器，被配置为通过CPU执行的程序将存储器保护信息指定给存储器空间，存储器访问控制装置被配置为确定是否允许根据存储器保护信息从CPU获取存储器访问请求;以及复位装置，被配置为根据从CPU输出的复位请求信号使存储在保护信息存储器中的存储器保护信息无效，CPU执行的程序的切换，复位请求信号基于CPU执行程序的状态。复位装置响应于CPU输出的复位请求信号，将保护信息存储器的多个保护设置寄存器的所有有效位存储区域设置为无效状态。

10. 发明授权

US09904631B2 Microcomputer and method for controlling memory access 有权
公开(公告)号：US09904631B2
公开(公告)日：2018-02-27
申请号：US15013606
申请日：2016-02-02
申请人： Renesas Electronics Corporation
发明人： Rika Ono , Hitoshi Suzuki
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F12/145 , G06F12/14 , G06F12/1441 , G06F12/1491 , G06F2212/1052
摘要： A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a CPU (Central Processing Unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.

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