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1. 发明授权

US07234037B2 Memory mapped Input/Output operations 有权
标题翻译：内存映射输入/输出操作
公开(公告)号：US07234037B2
公开(公告)日：2007-06-19
申请号：US10723044
申请日：2003-11-25
申请人： Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
发明人： Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
IPC分类号： G06F9/34
CPC分类号： G06F12/1475 , G06F9/30003 , G06F9/342 , G06F12/063
摘要： A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with the definition(s) of the z/Architecture; and wherein a process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
摘要翻译：一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第二指令，以根据z / Architecture的定义加载数据; 并且其中，处理发出所述第一指令和所述第二指令中的至少一个，从而使得所述存储器和所述负载中的至少一个与所述第一备用地址空间一起执行。

2. 发明授权

US07146482B2 Memory mapped input/output emulation 有权
标题翻译：内存映射输入/输出仿真
公开(公告)号：US07146482B2
公开(公告)日：2006-12-05
申请号：US10723506
申请日：2003-11-25
申请人： David F. Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
发明人： David F. Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
IPC分类号： G06F9/26
CPC分类号： G06F9/30003 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/342
摘要： A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.
摘要翻译：一种将存储器映射的输入输出操作管理到备用地址空间的方法，包括：执行指向与第一适配器相关联的机器的第一存储器映射输入输出备用地址空间的第一指令，以将与第一适配器相关联的资源分配给过程按照az / Architecture的定义; 其中所选择的过程将所述机器的问题状态中执行的加载和存储指令中的至少一个发出到所选择的资源的所选地址位置。该方法还包括确保所选择的资源对应于所分配的资源，并确定所选择的进程与分配资源的进程相对应。

3. 发明授权

US07552436B2 Memory mapped input/output virtualization 有权
标题翻译：内存映射输入/输出虚拟化
公开(公告)号：US07552436B2
公开(公告)日：2009-06-23
申请号：US10723405
申请日：2003-11-25
申请人： Frank William Brice, Jr. , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Damian L. Osisek , Donald W. Schmidt
发明人： Frank William Brice, Jr. , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Damian L. Osisek , Donald W. Schmidt
IPC分类号： G06F9/46 , G06F3/00
CPC分类号： G06F12/0292 , G06F9/45537 , G06F2212/206
摘要： A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
摘要翻译：一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出交替地址空间的第二指令，以根据z / Architecture的定义加载数据; 将与所述第一替代地址空间相关联的实际资源和虚拟资源中的至少一个分配给进程; 确保所选择的进程与分配资源的进程相对应。该过程发生第一指令和第二指令中的至少一个，从而导致使用第一替代地址空间执行存储和加载中的至少一个。

4. 发明授权

US07606965B2 Information handling system with virtualized I/O adapter ports 失效
标题翻译：具有虚拟化I / O适配器端口的信息处理系统
公开(公告)号：US07606965B2
公开(公告)日：2009-10-20
申请号：US11676555
申请日：2007-02-20
申请人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
发明人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
IPC分类号： G06F13/00 , G06F13/14 , G06F9/455 , G06F3/00
CPC分类号： G06F13/4022 , G06F13/102
摘要： A communication port of a communications interface of an information handling system comprises a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then issued requesting the communications interface to virtualize the communication port. In response to the second command, one or more virtual switches are then configured to connect to the communication port, each virtual switch including a plurality of virtual ports, such that the one or more virtual switches are configured in a manner sufficient to support the number of images of virtual ports indicated by the obtained information. Thereafter, upon request via issuance of a third command, a logical link is established between one of the virtual ports of one of the virtual switches and a communicating element of the information handling system.
摘要翻译：信息处理系统的通信接口的通信端口包括多个虚拟端口。发出第一命令以获得指示可由通信接口支持的虚拟端口的图像数量的信息。然后发出请求通信接口虚拟通信端口的第二命令。响应于第二命令，一个或多个虚拟交换机然后被配置为连接到通信端口，每个虚拟交换机包括多个虚拟端口，使得一个或多个虚拟交换机被配置为足以支持数量由所获得的信息指示的虚拟端口的图像。此后，根据通过发出第三命令的请求，在一个虚拟交换机的虚拟端口之一和信息处理系统的通信元件之间建立逻辑链路。

5. 发明授权

US07200704B2 Virtualization of an I/O adapter port using enablement and activation functions 有权
标题翻译：使用启用和激活功能虚拟化I / O适配器端口
公开(公告)号：US07200704B2
公开(公告)日：2007-04-03
申请号：US11100837
申请日：2005-04-07
申请人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
发明人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
IPC分类号： G06F13/00 , G06F13/173 , H04L12/00
CPC分类号： G06F13/4022 , G06F13/102
摘要： A method for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then issued requesting the communications interface to virtualize the communication port. In response to the second command, one or more virtual switches are then configured to connect to the communication port, each virtual switch including a plurality of virtual ports, such that the one or more virtual switches are configured in a manner sufficient to support the number of images of virtual ports indicated by the obtained information. Thereafter, upon request via issuance of a third command, a logical link is established between one of the virtual ports of one of the virtual switches and a communicating element of the information handling system.
摘要翻译：一种用于将信息处理系统的通信接口的通信端口配置成多个虚拟端口的方法。发出第一命令以获得指示可由通信接口支持的虚拟端口的图像数量的信息。然后发出请求通信接口虚拟通信端口的第二命令。响应于第二命令，一个或多个虚拟交换机然后被配置为连接到通信端口，每个虚拟交换机包括多个虚拟端口，使得一个或多个虚拟交换机被配置为足以支持数量由所获得的信息指示的虚拟端口的图像。此后，根据通过发出第三命令的请求，在一个虚拟交换机的虚拟端口之一和信息处理系统的通信元件之间建立逻辑链路。

6. 发明授权

US07581021B2 System and method for providing multiple virtual host channel adapters using virtual switches 有权
标题翻译：使用虚拟交换机提供多个虚拟主机通道适配器的系统和方法
公开(公告)号：US07581021B2
公开(公告)日：2009-08-25
申请号：US11100846
申请日：2005-04-07
申请人： Richard K. Errickson , David Craddock , Thomas A. Gregg , Donald W. Schmidt , Jeffrey M. Turner , Bruce M. Walk
发明人： Richard K. Errickson , David Craddock , Thomas A. Gregg , Donald W. Schmidt , Jeffrey M. Turner , Bruce M. Walk
IPC分类号： G06F15/173
CPC分类号： H04L49/35 , H04L49/30 , H04L49/358 , H04L49/70 , H04L67/1097
摘要： A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.
摘要翻译：提供网络的处理器节点，其包括一个或多个处理器和虚拟通道适配器。虚拟化通道适配器可操作以引用表以确定通信的目的地是否由虚拟化通道适配器支持。当目的地被支持通过硬件进行路由时，虚拟化信道适配器可操作以经由硬件将通信路由到虚拟化信道适配器的物理端口和逻辑端口中的至少一个。否则，当目的地不支持通过硬件进行路由时，虚拟化信道适配器可操作地将通过固件的通信路由到虚拟化信道适配器的虚拟端口。本文还提供了相应的方法和记录介质，用于执行这种方法。

7. 发明授权

US07058837B2 Method and system for providing a message-time-ordering facility 有权
标题翻译：提供消息时间排序设施的方法和系统
公开(公告)号：US07058837B2
公开(公告)日：2006-06-06
申请号：US10435970
申请日：2003-05-12
申请人： David A. Elko , Richard K. Errickson , Steven N. Goss , Dan F. Greiner , Carol B. Hernandez , Ronald M. Smith, Sr. , David H. Surman
发明人： David A. Elko , Richard K. Errickson , Steven N. Goss , Dan F. Greiner , Carol B. Hernandez , Ronald M. Smith, Sr. , David H. Surman
IPC分类号： G06F15/16 , G06F1/04 , G06F1/12 , H04J3/06 , H04L7/00 , H04L7/02 , H04L7/04
CPC分类号： G06F9/546
摘要： A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message. Sending the response includes marking the response with a second departure time-stamp responsive to the receiver system clock if the delay variable is equal to zero and transmitting the response to the sender system. The response is received at the sender system. Receiving the response includes delaying the processing of the response if the delay variable is equal to zero until the time on the sender system clock is greater than the second departure time-stamp and recording a time associated with the delaying the processing of the response in the delay variable.
摘要翻译：公开了一种提供消息时间排序设施的方法。该方法包括在发送者系统处发起消息的消息定时器排序设施。启动包括将延迟变量设置为零。响应于启动消息时间排序设施，该消息被发送到接收机系统。发送消息包括响应于发送者系统时钟的第一起始时间戳来标记消息并将消息发送到接收机系统。消息在接收机系统处被接收，接收包括延迟消息的处理，直到接收机系统时钟的时间大于第一个出发时间戳，并且记录与将消息的处理延迟相关联的时间延迟变量。响应于接收到该消息，对该消息的响应被发送到发送者系统。发送响应包括响应于接收机系统时钟的第二个出发时间戳来标记响应，如果延迟变量等于零并将响应发送到发送器系统。发送方系统收到响应。如果延迟变量等于0，则接收响应包括延迟响应的处理，直到发送方系统时钟的时间大于第二个出发时间戳，并记录与延迟处理响应相关的时间延迟变量。

8. 发明申请

US20080141058A1 SYSTEM, METHOD, AND ARTICLE OF MANUFACTURE FOR SYNCHRONIZING TIME OF DAY CLOCKS ON FIRST AND SECOND COMPUTERS 有权
标题翻译：第一台和第二台计时器同步时钟同步的系统，方法和制造
公开(公告)号：US20080141058A1
公开(公告)日：2008-06-12
申请号：US11873557
申请日：2007-10-17
申请人： David F. Craddock , Richard K. Errickson , Thomas A. Gregg , Bruce Marshall Walk
发明人： David F. Craddock , Richard K. Errickson , Thomas A. Gregg , Bruce Marshall Walk
IPC分类号： G06F1/14 , G06F15/16
CPC分类号： G06F1/14 , G04G5/00 , G04G7/00
摘要： A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.
摘要翻译：提供了分别在第一和第二计算机上同步第一和第二时钟的系统，方法和制品。第一和第二计算机具有分别具有第三和第四时钟的第一和第二网络接口卡。系统利用由第三和第四时钟产生的时间戳值来同步第一和第二时钟时钟。

9. 发明授权

US07330488B2 System, method, and article of manufacture for synchronizing time of day clocks on first and second computers 有权
标题翻译：用于在第一和第二计算机上同步时钟的系统，方法和制品
公开(公告)号：US07330488B2
公开(公告)日：2008-02-12
申请号：US11016465
申请日：2004-12-17
申请人： David F. Craddock , Richard K. Errickson , Thomas A. Gregg , Bruce Marshall Walk
发明人： David F. Craddock , Richard K. Errickson , Thomas A. Gregg , Bruce Marshall Walk
IPC分类号： H04J3/06
CPC分类号： G06F1/14 , G04G5/00 , G04G7/00
摘要： A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.
摘要翻译：提供了分别在第一和第二计算机上同步第一和第二时钟的系统，方法和制品。第一和第二计算机具有分别具有第三和第四时钟的第一和第二网络接口卡。系统利用由第三和第四时钟产生的时间戳值来同步第一和第二时钟时钟。

10. 发明授权

US08762125B2 Emulated multi-tasking multi-processor channels implementing standard network protocols 有权
标题翻译：仿真多任务多处理器通道实现标准网络协议
公开(公告)号：US08762125B2
公开(公告)日：2014-06-24
申请号：US12036986
申请日：2008-02-25
申请人： Richard K. Errickson , Thomas A. Gregg , John S. Houston , Ambrose A. Verdibello, Jr.
发明人： Richard K. Errickson , Thomas A. Gregg , John S. Houston , Ambrose A. Verdibello, Jr.
IPC分类号： G06F9/455 , G06F13/10 , G06F9/54 , H04L12/56
CPC分类号： G06F13/105 , G06F9/544 , G06F9/546 , H04L49/901
摘要： A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers.
摘要翻译：一种用于在多任务多处理器环境中模拟信道的计算机程序产品，装置和方法，包括识别具有用于多个物理信道中的每一个的相关联的物理信道标识符的多个物理信道，将来自多个用于生成多个仿真信道，多个仿真信道中的每一个具有虚拟信道标识符，在通信链路上映射多个仿真信道，从而生成仿真信道路径对于多个仿真信道中的每一个，为每个仿真信道的多个队列对链路缓冲器定义队列对链路缓冲器，并增加队列对链路缓冲器的数量。

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